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ATXMEGA128D4 датащи(PDF) 13 Page - ATMEL Corporation

номер детали ATXMEGA128D4
подробное описание детали  8/16-bit AVR XMEGA D4 Microcontroller
PDF  100 Pages
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производитель  ATMEL [ATMEL Corporation]
домашняя страница  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATXMEGA128D4 датащи(HTML) 13 Page - ATMEL Corporation

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8135G–AVR–08/10
XMEGA D4
7.4.3
EEPROM Data Memory
The XMEGA D4 devices have internal EEPROM memory for non-volatile data storage. It is
addressable either in a separate data space or it can be memory mapped into the normal data
memory space. The EEPROM memory supports both byte and page access.
7.5
Production Signature Row
The Production Signature Row is a separate memory section for factory programmed data. It
contains calibration data for functions such as oscillators and analog modules.
The production signature row also contains a device ID that identify each microcontroller device
type, and a serial number that is unique for each manufactured device. The device ID for the
available XMEGA A4 devices is shown in Table 7-1 on page 13. The serial number consist of
the production LOT number, wafer number, and wafer coordinates for the device.
The production signature row can not be written or erased, but it can be read from both applica-
tion software and external programming.
Table 7-1.
Device ID bytes for XMEGA D4 devices.
7.6
User Signature Row
The User Signature Row is a separate memory section that is fully accessible (read and write)
from application software and external programming. The user signature row is one flash page
in size, and is meant for static user parameter storage, such as calibration data, custom serial
numbers or identification numbers, random number seeds etc. This section is not erased by
Chip Erase commands that erase the Flash, and requires a dedicated erase command. This
ensures parameter storage during multiple program/erase session and on-chip debug sessions.
7.7
Flash and EEPROM Page Size
The Flash Program Memory and EEPROM data memory are organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 14 shows the Flash Program Memory organization. Flash write and erase
operations are performed on one page at the time, while reading the Flash is done one byte at
the time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant
bits in the address (FPAGE) give the page number and the least significant address bits
(FWORD) give the word in the page.
Device
Device ID bytes
Byte 2
Byte 1
Byte 0
ATxmega16D4
42
94
1E
ATxmega32D4
42
95
1E
ATxmega64D4
47
96
1E
ATxmega128D4
47
97
1E



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