LTC2655 datasheet(21/28 Pages) LINER

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LTC2655

2655f

OPERATION

Write Word Protocol

The master initiates communication with the LTC2655

with a START condition and a 7-bit slave address followed

by the Write bit (W) = 0. The LTC2655 acknowledges by

pulling the SDA pin low at the 9th clock if the 7-bit slave

address matches the address of the part (set by CA0, CA1

and CA2) or the global address. The master then transmits

three bytes of write data. The LTC2655 acknowledges each

byte of data by pulling the SDA line low at the 9th clock of

each data byte transmission. After receiving three com-

plete bytes of data, the LTC2655 executes the command

speciﬁed in the 24-bit input word. If more than three data

bytes are transmitted after a valid 7-bit slave address, the

LTC2655 does not acknowledge the extra bytes of data

(SDA is high during the 9th clock). The ﬁrst byte of the

input word consists of the 4-bit command followed by

the 4-bit address. The next two bytes consist of the 16-bit

data word. The 16-bit data word consists of the 16-bit, or

12-bit input code, MSB to LSB, followed by 0 or 4 don’t

care bits (LTC2655-16 and LTC2655-12 respectively). A

typical LTC2655 write transaction is shown in Figure 2.

The command (C3-C0) and address (A3-A0) assignments

are shown in Table 1. The ﬁrst four commands in the table

consist of write and update operations. A write operation

loads a 16-bit data word from the 32-bit shift register into

the input register. In an update operation, the data word

is copied from the input register to the DAC register and

converted to an analog voltage at the DAC output. The

update operation also powers up the DAC if it had been in

power-down mode. The data path and registers are shown

in the Block Diagram.

Power-Down Mode

For power-constrained applications, power-down mode

can be used to reduce the supply current whenever less

than four outputs are needed. When in power-down, the

buffer ampliﬁers, bias circuits and integrated reference

circuits are disabled, and draw essentially zero current.

The DAC outputs are put into a high-impedance state, and

the output pins are passively pulled to ground through

individual 80k resistors. Input- and DAC-register contents

are not disturbed during power-down.

Any channel or combination of channels can be put into

power-down mode by using command 0100b in combina-

tion with the appropriate DAC address, (

n). The integrated

reference is automatically powered down when external

reference mode is selected using command 0111b. In ad-

dition, all the DAC channels and the integrated reference

together can be put into power-down mode using the

Power-Down Chip command 0101b. For all power-down

commands the 16-bit data word is ignored, but still required

in order to complete a full communication cycle.

Normal operation resumes by executing any command

which includes a DAC update, in software as shown in

Table 1 or using the asynchronous LDAC pin. The selected

DAC is powered up as its voltage output is updated. When

a DAC which is in a powered-down state is powered up and

updated, normal settling is delayed. If less than four DACs

are in a powered-down state prior to the update command,

the power-up delay time is approximately 12μs. If on the

other hand, all four DACs and the integrated reference

are powered down, then the main bias generation circuit

block has been automatically shut down in addition to the

individual DAC ampliﬁers and the integrated reference.

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