AD5749

Rev. 0 | Page 21 of 28

Readback Operation

Readback mode is activated by selecting the correct device address

(A2, A1, A0) and then setting the R/W bit to 1. By default, the

SDO pin is disabled. After having addressed the AD5749 for a

read operation, setting R/W to 1 enables the SDO pin and SDO

has been clocked out on SDO, a rising edge on SYNC disables

(tristate) the SDO pin again. Status register data (see

)

and control register data are both available during the same

read cycle.

Table 9

The status bits comprise four read-only bits. They are used to

notify the user of specific fault conditions that occur, such as

an open circuit on the output, overtemperature error or an

interface error. If any of these fault conditions occur, a hardware

FAULT is also asserted low, which can be used as a hardware

interrupt to the controller.

See the Detailed Description of Features section for a full

explanation of fault conditions.

HARDWARE CONTROL

Hardware control is enabled by connecting the HW SELECT

pin to DVCC. In this mode, the R3, R2, R1, and R0 pins, in

conjunction with the RSET pin, are used to configure the

output range, as per Table 8.

In hardware mode, there is no status register. The fault conditions

(open circuit, and overtemperature) are available on Pin IFAULT

and Pin TEMP. If any one of these fault conditions is set, a low is

asserted on the specific fault pin. IFAULT and TEMP are open-

drain outputs and, therefore, can be connected together to allow the

user to generate one interrupt to the system controller to commun-

icate a fault. If hardwired in this way, it is not possible to isolate

which fault occurred in the system.

TRANSFER FUNCTION

The AD5749 consists of an internal signal conditioning block

that maps the analog input voltage to a programmed output

range. The available analog input range is 0 V to 4.096 V.

For all ranges, the AD5749 implements a straight linear

mapping function, where 0 V maps to the lower end of the

selected range and 4.096 V maps to the upper end of the

selected range.

Table 9. Input Shift Register Contents for a Read Operation—Status Register

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

A2

A1

A0

1

0

R3

R2

R1

R0

CLRSEL

OUTEN

RSET

PEC Error

OVER TEMP

IOUT Fault

Unused

Table 10. Status Bit Options

Bit

Description

PEC Error

This bit is set if there is an interface error detected by CRC-8 error checking. See the Detailed Description of Features section.

OVER TEMP

This bit is set if the AD5749 core temperature exceeds approximately 150°C.

IOUT Fault

This bit is set if there is an open circuit on the IOUT pin.