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© 2009 Semtech Corp.

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POWER MANAGEMENT

SC2596

Layout guidelines

pad should be add when PCB layout. Some thermal vias are required to connect the thermal pad to the PCB

ground layer. This will improve the thermal performance. Please refer to the recommanded landing pattern.

2) To increase the noise immunity, a ceramic capacitor of 100nF is required to decouple the V

shortest connection trace.

ceramic capacitor capacitor have to be used on the input power rail with shortest possible connection.

decouple the VTT pin.

5) The trace between VSENSE pin and VTT rail should be as short as possible and put a 10nF ~100nF capacitor

close this vsense pin.

Application Information (Cont.)

IO=380mA_Soure

0.00

10.00

20.00

30.00

40.00

50.00

60.00

70.00

80.00

90.00

10mR

50mR

100mR

200mohm

Cout=4.7uF

Cout=10uF

Cout=22uF

IO=380mA_SINK

-40.00

-20.00

0.00

20.00

40.00

60.00

80.00

100.00

120.00

10mR

50mR

100mR

200mohm

Cout=4.7uF

Cout=10uF

Cout=22uF

Figure 6: Bode Plot of an all ceramic capacitor application

Phase Margin vs External ESR

Application_5: Bode Plot of an all ceramic capacitor solution in Figure 5.

Figure 7: Phase margin vs external ESR values for different output ceramic capacitor values

The phase margin is 72° and the bandwidth is around 1MHz, where: AVCC=3.3V, PVCC=VDDQ=1.8V, VTT=0.9V,

IOUT=380mA, COUT=10uF & 100mhom. For this application, we further measured the corresponding phase

margins for different output capacitor values and ESR values at designed sourcing and sinking currents in

Figure 7.