SC653

17

SemPulse

The SemPulse single wire interface is used to enable or disable the device and configure all registers (see Figure 2). The

timing parameters refer to the digital I/O electrical specifications.

Address is set

Data is written

SPIF

Up to 32 rising edges

(0 to 31 pulses)

Up to 64 rising edges

(0 to 63 pulses)

Figure 2 — Uniform Timing Diagram for SemPulse Communication

Timing Example 1

In this example (see Figure 3), the slave chip receives a sequence of pulses to set the address and data, and the pulses

experience interrupts that cause the pulse width to be non-uniform. Note that as long as the maximum high and low

times are satisfied and the hold times are within specification, the data transfer is completed regardless of the number

of interrupts that delay the transmission.

Data written is

000011

SPIF

Address is set to

register 02h

Figure 3 — SemPulse Data Write with Non-Uniform Pulse Widths

Timing Example 2

In this example (see Figure 4), the slave chip receives two sets of pulses to set the address and data, but an interrupt

occurs during a pulse that causes it to exceed the minimum address hold time. The write is meant to be the value 03h

in register 05h, but instead it is interpreted as the value 02h written to register 02h. The extended pulse that is delayed

by the interrupt triggers a false address detection, causing the next pulse set to be interpreted as the data set. To avoid

any problems with timing, make sure that all pulse widths comply with their timing requirements as outlined in this

datasheet.

Data written is

000010

SPIF

Address is set to

register 02h

Interrupt

duration

Address is set to register

03h (address and data are

now out of order)

Figure 4 — Faulty SemPulse Data Write Due to Extended Interrupt Duration