APPLICATION INFORMATION

Typical Application

Designing with High-Speed Differential Signals

TPD2E009

Figure 13. TPD2E009 in Differential eSATA Interface

Figure 13 shows the board layout scheme for the D+/D– lines of a single differential pair. It allows the differential

signal pairs couple together right after they touch the ESD ports (pin 1 and pin 2) of the TPD2E009.

Layout considerations, such as package selection, trace routing, etc. must be taken into account while designing

the ESD clamp circuit for high-speed interface. Difficult routing can lead the designer to use vias or stubs in the

board traces, creating significant disruption in the line impedance in the high-speed signal path. Poor package

choice can force designer to route differential traces with unequal lengths and add the skew in the signals. It is

recommended to closely couple the differential traces to reduce the EMI interference.

The TPD2E009 can provide system level ESD protection to the high-speed differential ports (>6 Gbps data rate).

The flow-through package offers flexibility for board routing with traces up to 15 mills wide. Figure 14 and

Figure 15 show the board layout scheme for the D+/D– lines of a single differential pair. It allows the differential

signal pairs couple together right after they touch the ESD ports (pin 1 and pin 2) of the TPD2E009.

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