1

FEATURES

DESCRIPTION

PINOUT ASSIGNMENT

APPLICATIONS

1

8

2

7

3

6

4

5

Q

0

Q

0

Q

1

Q

1

V

CC

D

D

V

EE

SN65LVEL11

3.3 V ECL 1:2 Fanout Buffer

• 1:2 ECL Fanout Buffer

• Operating Range

The SN65LVEL11 is a fully differential 1:2 ECL fanout

buffer. The device includes circuitry to maintain a

–

known logic level when inputs are in open condition.

The

SN65LVEL11

is

functionally

equivalent

to

–

SN65EL11

with

improved

performance.

The

to –3.8V

SN65LVEL11 is housed in an industry standard

SOIC-8

package

and

is

also

available

in

the

• 5 ps Skew Between Outputs

TSSOP-8 package option.

• Support for Clock Frequencies > 2.0 GHz

• 265 ps Typical Propagation Delay

• Deterministic Output Value for Open Input

• Built-in Temperature Compensation

• Drop in Compatible to MC10LVEL11,

MC100LVEL11

• Built-In Input Pull Down Resistors

• Data and Clock Transmission Over Backplane

• Signaling Level Conversion

Table 1. Pin Description

PIN

FUNCTION

D, D

PECL/ECL data inputs

PECL/ECL outputs

Positive supply

Negative supply

PART NUMBER

PART MARKING

PACKAGE

LEAD FINISH

SN65LVEL11D

SN65LVEL11

SOIC

NiPdAu

SN65LVEL11DGK

SN65LVEL11

SOIC-TSSOP

NiPdAu

(1)

Leaded device options not initially available. Contact TI sales representative for further details.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2008, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.