S6B0708

64COM/128SEG GRAPHIC DRIVER FOR DOT MATRIX

LCD

12

DISPLAY DATA RAM (DDRAM)

The display data RAM stores pixel data for the LCD. It is a 128-column x 64-row addressable array as shown in

Table 4. The 64 rows are divided into 8 pages of 8 lines. Data is read from or written to the 8 lines of each page

directly through DB0 to DB7. The microprocessor reads data from and writes data to RAM through the I/O buffer.

Since the LCD controller operates independently, data can be written to RAM at the same time as the data is

being displayed, without causing a LCD flicker.

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

1

0

0

1

0

1

0

1

0

0

0

0

0

1

0

0

0

1

0

0

0

1

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

Display Data RAM

LCD Panel

Figure 2. RAM to LCD Panel Data Transfer