MC145532

MOTOROLA

4

DECODER OUTPUT — SHORT FRAME

Figure 7 shows the timing of the decoder output in short

frame mode.

The DDO will provide the 8–bit PCM word for the decoding

rate that was selected for this frame of data on the decoder

input pins. The data is loaded into the MC145532 during one

frame, decoded on the next frame, and read during the third

frame.

DECODER OUTPUT — LONG FRAME

Figure 8 shows the timing of the decoder output in long

frame mode. Note that at least eight bits are presented to the

output, provided that at least two falling edges of DDC are

seen while DOE is high. The enable can be used to extend

the LSB to a full DDC period and/or cause the eight bits of

data to be recirculated to the output pin until the enable falls.

STANDARDS INFORMATION

The following standards apply to the MC145532:

T1.301–1987 — 32 kbps ADPCM

T1.303–1988 — 24 kbps ADPCM

CCITT G.721–1988, G.723–1988, and G.726 — 32 kbps

and 24 kbps

CCITT, ITU–T, TIA, and EIA documents may be obtained

by contacting Global Engineering Documents in the USA at

(800) 854–7179, or internationally at (303) 397–7956.

Rating

Symbol

Value

Unit

DC Supply Voltage

VDD

– 0.5 to + 7.0

V

Voltage, Any Pin to VSS

V

– 0.5 to VDD + 0.5

V

DC Current, Any Pin

Iin

± 10

mA

Operating Temperature

TA

– 40 to + 85

°C

Storage Temperature

Tstg

– 85 to + 150

°C

Parameter

Symbol

Min

Max

Unit

DC Supply Voltage

VDD

4.50

5.50

V

Power Dissipation

PD

—

0.28

W

Parameter

Symbol

Min

Max

Unit

High Level Input Voltage

Mode, DOE, DDC, DDI, DIE, EIE, EDI, EDC, EOE

VIH

2.0

—

V

Low Level Input Voltage

Mode, DOE, DDC, DDI, DIE, EIE, EDI, EDC, EOE

VIL

—

0.8

V

High Level Input Voltage

RESET, APD, SPC

VIH

0.7 VDD

—

V

Low Level Input Voltage

RESET, APD, SPC

VIL

—

0.3 VDD

V

Input Current

Iin

—

± 1.0

µA

Input Capacitance

Cin

—

10

pF

High Level Output Voltage (IOH = – 2.0 mA)

DDO, EDO

VOH

4.6

—

V

Low Level Output Voltage (IOL = 2.0 MA)

DDO, EDO

VOL

—

0.4

V

Output Leakage Current (VDD = 5.5 V)

DDO, EDO

Ilkg

—

± 5.0

µA

Parameter

Min

Max

Unit

SPC Frequency

19.990

23

MHz

SPC Duty Cycle

45

55

%

This device contains circuitry to protect

against damage due to high static voltages or

electric fields; however, it is advised that

normal precautions be taken to avoid appli-

cation of any voltage higher than maximum

rated voltages to this high impedance circuit.

For proper operation it is recommended that

Vin and Vout be constrained to the range VSS ≤

(Vin or Vout) ≤ VDD.

Unused inputs must always be tied to an

appropriate logic voltage level (e.g., either VSS

or VDD).