12

Video ICs

BA7207AS / BA7207AK

(1) Recording system (REC)

The input to REC IN is passed through the 4.3MHz BPF-A to remove unwanted frequency components, and is flat-

tened by REC BELL which has an anti-bell characteristic. The flattened signal is wave-shaped by the limiter amplifer,

and processed by the divide-by-four and sync gate circuits. Finally, unwanted frequency components are removed

by the 1.1MHz BPF and the REC EQ prepares the signal for recording playback and the signal is output on REC

OUT. Refer to Fig. 3.

1

26

24

(

)

(

)

(

)

(

)

28

4.3MHz

BPF - A

REC

BELL

LIMAMP

1.1MHz

BPF

÷ 4

REC

SYNC

GATE

REC

EQ

AMP

RECOUT

BA7207AS

(BA7207AK)

100pF

Composite video signal

Fig. 3

33

27

31

40

(2) Playback system (PB)

The input to PB IN is passed through the 1.1MHz BPF to remove unwanted frequency components, and is flattened

by the PB EQ circuit. The amplitude of the flattened signal fixed by the 1st-stage limiter amplifier, and the frequency

is multiplied by four by the multiplier circuit. Unwanted frequency components generated by the multiplier circuit are

removed by the 2.2MHz BPF and 4.3MHz BPF-A. The signal is wave-shaped by the limiter amplifier, and has gate

applied to it by the sync gate circuit then is passed through the 4.3MHz BPF-B to remove unwanted frequency com-

ponents. The PB BELL circuit restores the original bell characteristic and the signal is output on PB OUT. Refer to

Fig. 4.

18

1.1MHz

BPF

PB

EQ

LPF

LIMAMP

2.2MHz

BPF

4.3MHz

BPF - A

× 2

× 2

AMP

BA7207AS

(BA7207AK)

RF chroma signal

24

26

6

8

11

PB

SYNC

GATE

AMP

AMP

PBOUT

LIMAMP

4.3MHz

BPF - B

PB

BELL

TRAP

fc 2.2MHz

Fig. 4

2

5

10

31

27

20

(

)

(

)

(

)

(

)

(

)

(

)

(3) Sync gate timing circuit

REC and PB SYNC gate operation is as follows. The gate closes closes in synchronous with the SYNC IN input

pulse during the synchronous signal pulse (SYNC) horizontal scan interval (64

µs period). During vertical retrace

(32

µS period), the input pulse period becomes shorter than the horizontal scan interval. This is detected by the built-

in vertical synchronous detector circuit which closes the gate. Refer to Fig. 5.

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Horizontal scan interval

Vertical retrace interval

4

µs

64

µs

32

µs

SYNCIN

REC / PBOUT

Fig. 5