7-29
RF9957
Rev C11 010622
7
Pin
Function
Description
Interface Schematic
1VCC1
Supply voltage for the LO flip-flop divider and limiting amp. This pin
may be connected in parallel with pins 2 and 3. It should be bypassed
by a 10nF capacitor. The trace length between the pin and the bypass
capacitor should be minimized. The ground side of the bypass capaci-
tor should connect immediately to ground plane. The part is designed
to work from a 2.7V to 3.3V supply.
2VCC2
Supply voltage for the bandgap, gain control bias circuitry, and AGC
stages 2, 3, and 4. This pin may be connected in parallel with pins 1
and 3. It should be bypassed by a 10nF capacitor. The trace length
between the pin and the bypass capacitor should be minimized. The
ground side of the bypass capacitor should connect immediately to
ground plane. The part is designed to work from a 2.7V to 3.3V supply.
3VCC3
Supply voltage for the FM and CDMA AGC input stages. This pin may
be connected in parallel with pins 1 and 2. It should be bypassed by a
10nF capacitor. The trace length between the pin and the bypass
capacitor should be minimized. The ground side of the bypass capaci-
tor should connect immediately to ground plane. The part is designed
to work from a 2.7V to 3.3V supply.
4
CDMA IN+
CDMA Balanced Input pin. This pin is internally DC biased and should
be DC blocked if connected to a device with a DC level present. For sin-
gle-ended input operation, one pin is used as an input and the other
CDMA input is AC coupled to ground. The balanced input impedance is
2.4k
Ω, while the single-ended input impedance is 1.2kΩ.
5
CDMA IN-
Same as pin 4, except complementary input.
See pin 4.
6GND
Ground connection. Keep traces physically short and connect immedi-
ately to ground plane for best performance.
7GND
Same as pin 6.
8FM IN+
FM Balanced Input pin. This pin is internally DC biased and should be
DC blocked if connected to a device with DC present. For single-ended
input operation, one pin is used as an input and the other FM input is
AC coupled to ground. The balanced input impedance is 2.4k
Ω, while
the single-ended input impedance is 1.2k
Ω.
9FM IN-
Same as pin 8, except complementary input.
See pin 8.
10
BG OUT
Bandgap Voltage Reference. This voltage, constant over temperature
and supply variation, is used to bias internal circuits. A 10nF external
bypass capacitor is required. The trace length between the pin and the
bypass capacitor should be minimized. The ground side of the bypass
capacitor should connect immediately to ground plane.
11
DEC
AGC decoupling pin. An external bypass capacitor of 10nF capacitor is
required. The trace length between the pin and the bypass capacitor
should be minimized. The ground side of the bypass capacitor should
connect immediately to ground plane.
12
LO-
LO Balanced Input pin. This pin is internally DC biased and should be
DC blocked if connected to a device with DC present. For single-ended
input operation, one pin is used as an input and the other LO input is
AC coupled to ground. The frequency of the signal applied to these
pins is internally divided by a factor of 2, hence the carrier frequency for
the modulator becomes one half of the applied frequency. The single-
ended input impedance is 400
Ω (balanced is 800Ω). The LO input may
be driven single-ended but balanced provides optimum gain and phase
balance.
13
LO+
Same as pin 12, except complementary input.
See pin 12.
1200
Ω
1200
Ω
CDMA IN+
BIAS
BIAS
CDMA IN-
1200
Ω
1200
Ω
FM IN+
BIAS
BIAS
FM IN-
400
Ω
400
Ω
LO-
BIAS
BIAS
LO+
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