8-108
RF2486
Rev A7 010717
8
Application Schematic
1.96GHz, 210MHz IF
Pin
Function
Description
Interface Schematic
20
LNA OUT
LNA output pin. This is an open-collector output. This pin is typically
connected to pin 22 through a bias/matching inductor. This inductor, in
conjunction with a series blocking/matching capacitor, forms a match-
ing network to the 50
Ω image filter and provides bias (see application
schematic). The LNA’s IP3 may be increased 10dB by connecting pin
20 to VCC through the inductor. The LNA’s current then increases by
10mA. Other in-between IP3 versus ICC trade-offs may be made by
connecting resistance values between VCC and the matching inductor.
The two reference points for consideration are with 150
Ω used, which
is what connection to pin 22 achieves, the input IP3 is +5.5dBm and the
LNA ICC is 5mA. Using no resistance, the input IP3 is +15.5 dBm and
the LNA ICC is 15 mA. Desired operating points in between these val-
ues may be roughly interpolated.
21
GND8
Same as pin 17.
22
VCC4
Output supply voltage for the LNA output (pin 20). This pin is typically
connected to pin 20 through a bias/matching inductor (see application
schematic). External RF bypassing is required. The trace length
between the pin and the bypass capacitor should be minimized. The
ground side of the bypass capacitor should connect immediately to
ground plane.
See pin 2.
23
GND9
Same as pin 17.
24
NC
No connection. This pin may be grounded (recommended) or left open.
LNA OUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
2pF
22 pF
BUF ENBL
1k
Ω
100 pF
2.7 nH
R2
VCC
22 pF
4.7
µF
22 pF
LNA2 IN
1.8 nH
22 pF
MIX IN
LNA OUT
See evaluation
board
1nF
22 pF
LO OUT
470 nH
470 nH
470 nH
100 pF
V
CC
SAW
Filter
IF SAW
Filter
1
2
LO IN
V
CC
1nF
22 pF
22 pF
1nF
V
CC
1nF
22 pF
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