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POWER MANAGEMENT

SC615A

Layout Guidelines

The following layout is suggested for a two-layer design.

The capacitors C1 and C2 are the bucket capacitors and

each conducts the full load current of up to 500mA pulsed

for one half clock cycle. C3 is the output decoupling ca-

pacitor placed near the SC615A VOUT pin. C4 is the input

decoupling capacitor placed near the SC615A VIN pin.

Multiple vias should be used whenever it is necessary to

change layers on nets connecting to pins VIN, VOUT, GND,

C1-, C1+, C2- and C2+. Resistor R1 is routed with a very

low resistance connection between R1 and GND pin 3.

The sense trace between Pin 6 and R1 is routed around

the ground vias, allowing the shortest ground return path

Bottom Copper

Top Copper

possible. The sense trace is connected to R1 at the positive

terminal pad for the most accurate output possible.

The bottom copper layer is mostly a ground plane with no

obstructions between the ground vias. The smaller rect-

angle to the left connects the input power to VIN pin 1 and

input capacitor C4. The two traces at the lower left are for

logic inputs FLASH and CTRL. The trace to the right is the

ISET pin “sense” trace. The sense trace is routed out of

the path of the returning ground current.