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T =25 C,

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High-Speed Mode

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Cross Coupling, Spur Suppression, and Noise Rejection

CDCE906

SCAS814H – NOVEMBER 2005 – REVISED DECEMBER 2007

The TI Pro Clock software automatically calculates the PLL parameter for jitter-optimized performance.

Cross-Coupling in ICs occurs through interactions between several parts of the chip such as between output

stages, metal lines, bond wires, substrate, etc. The coupling can be capacitive, inductive and resistive (ohmic)

induced by output switching, leakage current, ground bouncing, power supply transients, etc.

The CDCE906 is designed using the RFSiGe process technology. This process gives excellent performance in

linearity, low power consumption, best-in-class noise performance and good isolation characteristics between the

on-chip components.

The good isolation is a major benefit of the RFSiGe process because it minimizes the coupling effect. Even if all

three PLLs are active and all outputs are on, the noise suppression is well above 50 dB. Figure 31 and Figure 32

show an example of noise coupling, spur-suppression, and power supply noise rejection of CDCE906. Die

respective measurement conditions are shown in Figure 31 and Figure 32.

Copyright © 2005–2007, Texas Instruments Incorporated

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Product Folder Link(s): CDCE906