SC412AEVB datasheet(14/22 Pages) SEMTECH

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SC412A

POWER MANAGEMENT

Layout Guidelines (continued)

SC412A ESR Requirements

The constant on-time control used in the SC412A regulates

the valley of the output ripple voltage. This signal consists of

a term generated by the output ESR of the capacitor and a

term based on the increase in voltage across the capacitor

due to charging and discharging during the switching cycle.

The minimum ESR is set to generate the required ripple

voltage for regulation. For most applications the minimum

ESR ripple voltage is dominated by PCB layout and the

properties of SP or POSCAP type output capacitors. For

applications using ceramic output capacitors, the absolute

minimum ESR must be considered. If the ESR is low enough

the ripple voltage is dominated by the charging of the output

capacitor. This ripple voltage lags the on-time due to the

LC poles and can cause double pulsing if the phase delay

exceeds the off-time of the converter. To prevent double

pulsing, the ripple voltage present at the FB pin should be

10-15mV minimum over the on-time interval.

Dropout Performance

The output voltage adjust range for continuous-conduction

operation is limited by the ﬁxed 350nS (typical) Minimum

Off-time One-shot. When working with low input voltages,

the duty-factor limit must be calculated using worst-case

values for on and off times.

The IC duty-factor limitation is given by:

ON(MIN)

DUTY = ————————

ON(MIN) + TOFF(MAX)

Be sure to include inductor resistance and MOSFET on-

state voltage drops when performing worst-case dropout

duty-factor calculations.

SC412A System DC Accuracy (VOUT Controller)

Three factors affect VOUT accuracy: the trip point of the

FB error comparator, the switching frequency variation

with line and load, and the external resistor tolerance. The

error comparator offset is trimmed so that it trips when the

feedback pin is 0.75V, 1%.

The on-time pulse in the SC412A is calculated to give a

pseudo-ﬁxed frequency of 325kHz. Nevertheless, some

frequency variation with line and load is expected. This

variation changes the output ripple voltage. Because con-

stant on-time converters regulate to the valley of the output

ripple, ½ of the output ripple appears as a DC regulation

error. For example, If the output ripple is 50mV with VIN =

6 volts, then the measured DC output will be 25mV above

the comparator trip point. If the ripple increases to 80mV

with VIN = 25 volts, then the measured DC output will be

40mV above the comparator trip. The best way to minimize

this effect is to minimize the output ripple.

To compensate for valley regulation it is often desirable

to use passive droop. Take the feedback directly from the

output side of the inductor, placing a small amount of trace

resistance between the inductor and output capacitor. This

trace resistance should be optimized so that at full load the

output droops to near the lower regulation limit. Passive

droop minimizes the required output capacitance because

the voltage excursions due to load steps are reduced.

The use of 1% feedback resistors contributes up to 1% er-

ror. If tighter DC accuracy is required use 0.1% resistors.

The output inductor value may change with current. This

will change the output ripple and thus the DC output volt-

age. The output ESR also affects the ripple and thus the

DC output voltage.

Switching Frequency Variations

The switching frequency will vary somewhat due to line and

load conditions. The line variations are a result of a ﬁxed

offset in the on-time one-shot, as well as unavoidable delays

in the external MOSFET switching. As VBAT increases, these

factors make the actual DH on-time slightly longer than the

idealized on-time. The net effect is that frequency tends

to falls slightly as with increasing input voltage.

The load variations are due to losses in the power train

due to IR drop and switching losses. For a conventional

PWM constant-frequency topology, as load increases the

duty cycle also increases slightly to compensate for IR and

switching losses in the MOSFETs and inductor. A constant

on-time topology must also overcome the same losses

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