SC403 datasheet(17/32 Pages) SEMTECH

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SC403

Note that this control method regulates the valley of the

output ripple voltage, not the DC value. The DC output

voltage V

OUT is offset by the output ripple according to the

following equation.

RIPPLE

OUT

When a large capacitor is placed in parallel with R1 (C

TOP)

OUT is shown by the following equation.

TOP

RIPPLE

OUT

)

(

Enable and Power Save Input

The EN/PSV input is used to enable or disable the switch-

ing regulator and the LDO.When EN/PSV is low (grounded),

the switching regulator is off and in its lowest power state.

When off, the output of the switching regulator soft-dis-

charges the output into a 15Ω internal resistor via the V

OUT

pin. When EN/PSV is allowed to float, the pin voltage will

float to 33% of the voltage at VDD. The switching regula-

tor turns on with PSAVE (power save) disabled and all

switching is in forced continuous mode.

When EN/PSV is high (above 45% of the voltage at VDD),

the switching regulator turns on with ultrasonic power-

save enabled. The ultrasonic PSAVE operation maintains a

minimum switching frequency of 25kHz, for applications

with stringent audio requirements.

Forced Continuous Mode Operation

The SC403 operates the switcher in FCM (Forced

Continuous Mode) by floating the EN/PSV pin (see Figure

4). In this mode one of the power MOSFETs is always on,

with no intentional dead time other than to avoid cross-

conduction. This feature results in uniform frequency

across the full load range with the trade-off being poor

efficiency at light loads due to the high-frequency switch-

ing of the MOSFETs. DH is the gate signal driving the

upper MOSFET. DL is the lower gate signal driving the

lower MOSFET.

FB Ripple

Voltage (VFB)

FB threshold

Inductor

Current

DC Load Current

DH on-time is triggered when

VFB reaches the FB Threshold.

(750mV)

On-time

(TON)

DL drives high when on-time is completed.

DL remains high until VFB falls to the FB threshold.

Figure 4 — Forced Continuous Mode Operation

Ultrasonic PSAVE Operation

The SC403 provides ultrasonic PSAVE operation at light

loads, with the minimum operating frequency fixed at

25kHz. This is accomplished using an internal timer that

monitors the time between consecutive high-side gate

pulses. If the time exceeds 40µs, DL drives high to turn the

low-side MOSFET on. This draws current from V

OUT through

the inductor, forcing both V

OUT and VFB to fall. When VFB

drops to the 750mV threshold, the next DH on-time is trig-

gered. After the on-time is completed the high-side

MOSFET is turned off and the low-side MOSFET turns on.

The low-side MOSFET remains on until the inductor

current ramps down to zero, at which point the low-side

MOSFET is turned off.

Applications Information (continued)

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