SC121 datasheet(18/23 Pages) SEMTECH

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SC121

duty cycle must remain between 20% and 90% for the

device to operate within specification.

Note that startup with a regulated active load is not the

same as startup with a resistive load. The resistive load

output current increases proportionately as the output

voltage rises until it reaches programmed V

OUT

LOAD

, while

a regulated active load presents a constant load as the

output voltage rises from 0V to programmed V

OUT

. Note

also that if the load applied to the output exceeds an

applicable V

OUT

–dependent startup current limit or duty

cycle limit, the criterion to advance to the next startup

stage may not be achieved. In this situation startup may

pause at a reduced output voltage until the load is reduced

further.

Output Overload and Recovery

The PWM steady state duty cycle is determined by

D = 1 – (V

OUT

), but must be somewhat greater in prac-

tice to overcome dissipative losses. As the output load

increases, the dissipative losses also increase. The PWM

controller must increase the duty cycle to compensate.

Eventually, one of two overload conditions will occur,

determined by V

, V

OUT

, and the overall dissipative losses

due to the output load current. Either the maximum duty

cycle of 90% will be reached or the n-channel FET 1.2A

(nominal) peak current limit will be reached, which effec-

tively limits the duty cycle to a lower value. Above that

load, the output voltage will decrease rapidly and in

reverse order the startup current limits will be invoked as

the output voltage falls through its various voltage thresh-

olds. How far the output voltage drops depends on the

load voltage vs. current characteristic.

A reduction in input voltage, such as a discharging battery,

will lower the load current at which overload occurs.

Lower input voltage increases the duty cycle required to

produce a given output voltage. And lower input voltage

also increases the input current to maintain the input

power, which increases dissipative losses and further

increases the required duty cycle. Therefore an increase in

load current or a decrease in input voltage can result in

output overload. Please refer to the Max. I

OUT

vs. V

Typical

Characteristics plots for the condition that best matches

the application.

Once an overload has occurred, the load must be

decreased to permit recovery. The conditions required for

overload recovery are identical to those required for suc-

cessful initial startup.

Component Selection

The SC121 provides optimum performance when a 4.7μH

inductor is used with a 10μF output capacitor. Different

component values can be used to modify input current or

output voltage ripple, improve transient response, or to

reduce component size or cost.

Inductor Selection

The inductance value primarily affects the amplitude of

inductor peak-to-peak current ripple (

ΔI

). Reducing

inductance increases

ΔI

and raises the inductor peak

current, I

L-max

= I

L-avg

ΔI

/2, where I

L-avg

is the inductor

current averaged over a full on/off cycle. I

L-max

is subject to

the n-channel FET current limit I

LIM(N)

, therefore reducing

the inductance may lower the output overload current

threshold. Increasing

ΔI

also lowers the inductor

minimum current, I

L-min

= I

L-avg

–

ΔI

/2, thus raising the load

current threshold below which inductor negative–peak

current becomes zero.

Equating input power to output power and noting that

input current is equal to inductor current, average the

inductor current over a full PWM switching cycle to

obtain

OUT

avg

where

η is efficiency.

Neglecting the n-channel FET R

DS-ON

and the inductor DCR,

for duty cycle D, and with T = 1/f

osc

This is the change in I

during the on-state. During the

off-state, again neglecting the p-channel FET R

DS-ON

and

the inductor DCR,

OUT

off

Applications Information (continued)

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