Given the typical thermal resistance from junction to case to

be 1.9 °C/W. Use the 85°C power dissipation curves in the

Typical Performance Characteristics section to estimate the

P

it is 0.52W.

θ

To reach

θ

fectively. With no airflow and no external heat, a good esti-

mate of the required board area covered by 1 oz. copper on

both the top and bottom metal layers is:

θ

As a result, approximately 6 square cm of 1 oz copper on top

and bottom layers is required for the PCB design. Additional

area will decrease die temperature proportionately. The PCB

copper heat sink must be connected to the exposed pad. Ap-

proximately thirty six, 10mils (254

μm) thermal vias spaced

59mils (1.5 mm) apart must connect the top copper to the

bottom copper. For an example of a high thermal performance

PCB layout of approximately 31 square cm area. Refer to the

Evaluation Board application note AN-2024. For more infor-

mation on thermal design see AN-2020 and AN-2026.

PC BOARD LAYOUT GUIDELINES

PC board layout is an important part of DC-DC converter de-

sign. Poor board layout can disrupt the performance of a DC-

DC converter and surrounding circuitry by contributing to EMI,

ground bounce and resistive voltage drop in the traces. These

can send erroneous signals to the DC-DC converter resulting

in poor regulation or instability. Good layout can be imple-

mented by following a few simple design rules.

30114611

1. Minimize area of switched current loops.

From an EMI reduction standpoint, it is imperative to minimize

the high di/dt paths during PC board layout. The high current

loops that do not overlap have high di/dt content that will

cause observable high frequency noise on the output pin if

the input capacitor (Cin1) is placed at a distance away from

the LMZ14201. Therefore place C

the LMZ14201 VIN and GND exposed pad. This will minimize

the high di/dt area and reduce radiated EMI. Additionally,

grounding for both the input and output capacitor should con-

sist of a localized top side plane that connects to the GND

exposed pad (EP).

2. Have a single point ground.

The ground connections for the feedback, soft-start, and en-

able components should be routed to the GND pin of the

device. This prevents any switched or load currents from

flowing in the analog ground traces. If not properly handled,

poor grounding can result in degraded load regulation or er-

ratic output voltage ripple behavior. Provide the single point

ground connection from pin 4 to EP.

3. Minimize trace length to the FB pin.

Both feedback resistors, R

capacitor C

the FB node is high impedance, maintain the copper area as

small as possible. The trace are from R

should be routed away from the body of the LMZ14201 to

minimize noise.

4. Make input and output bus connections as wide as

possible.

This reduces any voltage drops on the input or output of the

converter and maximizes efficiency. To optimize voltage ac-

curacy at the load, ensure that a separate feedback voltage

sense trace is made to the load. Doing so will correct for volt-

age drops and provide optimum output accuracy.

5. Provide adequate device heat-sinking.

Use an array of heat-sinking vias to connect the exposed pad

to the ground plane on the bottom PCB layer. If the PCB has

a plurality of copper layers, these thermal vias can also be

employed to make connection to inner layer heat-spreading

ground planes. For best results use a 6 x 6 via array with

minimum via diameter of 10mils (254

μm) thermal vias spaced

59mils (1.5 mm). Ensure enough copper area is used for heat-

sinking to keep the junction temperature below 125°C.

Additional Features

OUTPUT OVER-VOLTAGE COMPARATOR

The voltage at FB is compared to a 0.92V internal reference.

If FB rises above 0.92V the on-time is immediately terminat-

ed. This condition is known as over-voltage protection (OVP).

It can occur if the input voltage is increased very suddenly or

if the output load is decreased very suddenly. Once OVP is

activated, the top MOSFET on-times will be inhibited until the

condition clears. Additionally, the synchronous MOSFET will

remain on until inductor current falls to zero.

CURRENT LIMIT

Current limit detection is carried out during the off-time by

monitoring the current in the synchronous MOSFET. Refer-

ring to the Functional Block Diagram, when the top MOSFET

is turned off, the inductor current flows through the load, the

PGND pin and the internal synchronous MOSFET. If this cur-

rent exceeds 2.0 (typical) the current limit comparator dis-

ables the start of the next on-time period. The next switching

cycle will occur only if the FB input is less than 0.8V and the

inductor current has decreased below 2.0A. Inductor current

is monitored during the period of time the synchronous MOS-

FET is conducting. So long as inductor current exceeds 2.0A,

further on-time intervals for the top MOSFET will not occur.

Switching frequency is lower during current limit due to the

longer off-time. It should also be noted that current limit is

dependent on both duty cycle and temperature as illustrated

in the graphs in the typical performance section.

THERMAL PROTECTION

The junction temperature of the LMZ14201 should not be al-

lowed to exceed its maximum ratings. Thermal protection is

implemented by an internal Thermal Shutdown circuit which

activates at 165 °C (typ) causing the device to enter a low

power standby state. In this state the main MOSFET remains

off causing V

discharged to ground. Thermal protection helps prevent

catastrophic failures for accidental device overheating. When

the junction temperature falls back below 145 °C (typ Hyst =

20 °C) the SS pin is released, V

operation resumes.

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