CCM and DCM Operating Modes

V

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The approximate formula for determining the DCM/CCM

boundary is as follows:

I

Following is a typical waveform showing the boundary condi-

tion.

Transition Mode Operation

V

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The inductor internal to the module is 10

μH. This value was

chosen as a good balance between low and high input voltage

applications. The main parameter affected by the inductor is

the amplitude of the inductor ripple current (I

calculated with:

I

Where V

mined from equation 10.

If the output current I

I

aware that the lower peak of I

eration is required.

POWER DISSIPATION AND BOARD THERMAL

REQUIREMENTS

For the design case of V

thermal resistance from case to ambient of:

θ

Given the typical thermal resistance from junction to case to

be 1.9 °C/W .Use the 85°C power dissipation curves in the

Typical Performance Characteristics section to estimate the

P

it is 1.2W

θ

To reach

θ

effectively. With no airflow and no external heat, a good esti-

mate of the required board area covered by 1 oz. copper on

both the top and bottom metal layers is:

θ

As a result, approximately 15.9 square cm of 1 oz copper on

top and bottom layers is required for the PCB design. The

PCB copper heat sink must be connected to the exposed pad.

Approximately thirty six, 10 mils (254

μm) thermal vias spaced

59 mils (1.5 mm) apart must connect the top copper to the

bottom copper. For an example of a high thermal performance

PCB layout, refer to the demo board application note

AN-2024.

PC BOARD LAYOUT GUIDELINES

PC board layout is an important part of DC-DC converter de-

sign. Poor board layout can disrupt the performance of a DC-

DC converter and surrounding circuitry by contributing to EMI,

ground bounce and resistive voltage drop in the traces. These

can send erroneous signals to the DC-DC converter resulting

in poor regulation or instability. Good layout can be imple-

mented by following a few simple design rules.

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1. Minimize area of switched current loops.

From an EMI reduction standpoint, it is imperative to minimize

the high di/dt current paths during PC board layout. The high

current loops that do not overlap have high di/dt content that

will cause observable high frequency noise on the output pin

if the input capacitor C

LMZ12002. Therefore physically place C

sible to the LMZ12002 VIN and GND exposed pad. This will

minimize the high di/dt area and reduce radiated EMI. Addi-

tionally, grounding for both the input and output capacitor

should consist of a localized top side plane that connects to

the GND exposed pad (EP).

2. Have a single point ground.

The ground connections for the feedback, soft-start, and en-

able components should be routed to the GND pin of the

device. This prevents any switched or load currents from

flowing in the analog ground traces. If not properly handled,

poor grounding can result in degraded load regulation or er-

ratic output voltage ripple behavior. Provide the single point

ground connection from pin 4 to EP.

3. Minimize trace length to the FB pin.

Both feedback resistors, R

capacitor C

the FB node is high impedance, maintain the copper area as

small as possible. The trace are from R

13

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