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TUSB3210 датащи(PDF) 35 Page - Texas Instruments |
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TUSB3210 датащи(HTML) 35 Page - Texas Instruments |
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35 / 45 page ![]() www.ti.com 2.10.2 I2CADR: I 2C Address Register 2.10.3 I2CDAI: I 2C Data-Input Register 2.10.4 I2CDAO: I 2C Data-Output Register 2.11 Read/Write Operations 2.11.1 Read Operation (Serial EEPROM) TUSB3210 Universal Serial Bus General-Purpose Device Controller SLLS466F – FEBRUARY 2001 – REVISED AUGUST 2007 This register holds the device address and the read/write command bit. 7 6 5 4 3 2 1 0 A6 A5 A4 A3 A2 A1 A0 R/W R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 0 R/W 0 Read/write command bit R/W = 0 Write operation R/W = 1 Read operation 7–1 A[6:0] 000 0000 Seven address bits for device addressing This register holds the received data from an external device. 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/O R/O R/O R/O R/O R/O R/O R/O BIT NAME RESET FUNCTION 7–0 D[7:0] 0 8-bit input data from an I2C device This register holds the data to be transmitted to an external device. Writing to this register starts the transfer on the SDA line. 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 7–0 D[7:0] 0 8-bit output data to an I2C device A serial read requires a dummy byte write sequence to load in the 16-bit data word address. Once the device address word and data address word are clocked out and acknowledged by the device, the MCU starts a current address sequence. The following describes the sequence of events to accomplish this transaction: Device Address + EEPROM [High Byte] 1. The MCU sets I2CSTA[SRD] = 0.This prevents the I2C controller from generating a stop condition after the content of the I2CDAI register is received. 2. The MCU sets I2CSTA[SWR] = 0. This prevents the I2C controller from generating a stop condition after the content of the I2CDAO register is transmitted. 3. The MCU writes the device address (R/W bit = 0) to the I2CADR register (write operation). 4. The MCU writes the high byte of the EEPROM address into the I2CDAO register, starting the transfer on the SDA line. 5. The TXE bit in I2CSTA is cleared, indicating busy. 6. The content of the I2CADR register is transmitted to the EEPROM (preceded by start condition on Submit Documentation Feedback Functional Description 35 |
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