AM1707 datasheet(95/199 Pages) TI

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Receive Logic

Clock/Frame Generator

State Machine

Clock Check and

Serializer 0

Serializer 1

Serializer y

GIO

Control

DIT RAM

384 C

384 U

Optional

Transmit

Formatter

Receive

Formatter

Transmit Logic

Clock/Frame Generator

State Machine

McASPx (x = 0, 1, 2)

Peripheral

Configuration

Bus

McASP

DMA Bus

(Dedicated)

AHCLKRx

ACLKRx

AFSRx

AMUTEINx

AMUTEx

AFSXx

ACLKXx

AHCLKXx

AXRx[0]

AXRx[1]

AXRx[y]

Pins

Function

Receive Master Clock

Receive Bit Clock

Receive Left/Right Clock or Frame Sync

Transmit Master Clock

Transmit Bit Clock

Transmit Left/Right Clock or Frame Sync

Transmit/Receive Serial Data Pin

Error Detection

The McASPs DO NOT have

dedicated AMUTEINx pins.

AM1707

www.ti.com

SPRS637A – FEBRUARY 2010 – REVISED APRIL 2010

6.17 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)

The McASP serial port is specifically designed for multichannel audio applications. Its key features are:

•

Flexible clock and frame sync generation logic and on-chip dividers

•

Up to sixteen transmit or receive data pins and serializers

•

Large number of serial data format options, including:

–

TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst)

–

Time slots of 8,12,16, 20, 24, 28, and 32 bits

–

First bit delay 0, 1, or 2 clocks

–

MSB or LSB first bit order

–

Left- or right-aligned data words within time slots

•

DIT Mode (optional) with 384-bit Channel Status and 384-bit User Data registers

•

Extensive error checking and mute generation logic

•

All unused pins GPIO-capable

•

Transmit & Receive FIFO Buffers for each McASP. Allows the McASP to operate at a higher sample

rate by making it more tolerant to DMA latency.

•

Dynamic Adjustment of Clock Dividers

–

Clock Divider Value may be changed without resetting the McASP

The three McASPs on the device are configured with the following options:

Table 6-43. McASP Configurations(1)

Module

Serializers

AFIFO

DIT

Pins

64 Word RX

McASP0

AXR0[15:0], AHCLKR0, ACLKR0, AFSR0, AHCLKX0, ACLKX0, AFSX0, AMUTE0

64 Word TX

64 Word RX

AXR1[11:10], AXR1[8:0], AHCLKR1, ACLKR1, AFSR1, AHCLKX1, ACLKX1, AFSX1,

McASP1

64 Word TX

AMUTE1

16 Word RX

McASP2

AXR2[3:0], AHCLKR2, ACLKR2, AFSR2, AHCLKX2, ACLKX2, AFSX2, AMUTE2

16 Word TX

(1)

Pins available are the maximum number of pins that may be configured for a particular McASP; not including pin multiplexing.

Figure 6-33. McASP Block Diagram

Peripheral Information and Electrical Specifications

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