EPC4 datasheet(18/34 Pages) ALTERA

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Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Functional Description

Configuration Handbook (Complete Two-Volume Set)

Altera Corporation

Real-Time Decompression

Enhanced configuration devices support on-chip real time decompression of

configuration data. FPGA configuration data is compressed by the Quartus II

software and stored in the enhanced configuration device. During configuration, the

decompression engine inside the enhanced configuration device will decompress or

expand configuration data. This feature increases the effective-configuration density

of the enhanced configuration device up to 7, 15, or 30 Mbits in the EPC4, EPC8, and

EPC16, respectively.

The enhanced configuration device also supports a parallel 8-bit data bus to the FPGA

to reduce configuration time. However, in some cases, the FPGA data-transfer time is

limited by the flash-read bandwidth. For example, when configuring an APEX II

device in FPP (byte-wide data per cycle) mode at a configuration speed of 66 MHz,

the FPGA write bandwidth is equal to 8 bits × 66 MHz = 528 Mbps. The flash read

interface, however, is limited to approximately 10 MHz (since the flash access time is

~90 ns). This translates to a flash-read bandwidth of

16 bits × 10 MHz = 160 Mbps. Hence, the configuration time is limited by the

flash-read time.

When configuration data is compressed, the amount of data that needs to be read out

of the flash is reduced by about 50%. If 16 bits of compressed data yields 30 bits of

uncompressed data, the flash-read bandwidth increases to 30 bits × 10 MHz =

300 Mbps, reducing overall configuration time.

You can enable the controller's decompression feature in the Quartus II software,

Configuration Device Options

window by turning on Compression Mode.

1 The decompression feature supported in the enhanced configuration devices is

different from the decompression feature supported by the Stratix II FPGAs and the

Cyclone series. When configuring Stratix II FPGAs or the Cyclone series using

enhanced configuration devices, Altera recommends enabling decompression in

Stratix II FPGAS or the Cyclone series only for faster configuration.

The compression algorithm used in Altera devices is optimized for FPGA

configuration bitstreams. Since FPGAs have several layers of routing structures (for

high performance and easy routability), large amounts of resources go unused. These

unused routing and logic resources as well as un-initialized memory structures result

in a large number of configuration RAM bits in the disabled state. Altera's proprietary

compression algorithm takes advantage of such bitstream qualities.

The general guideline for effectiveness of compression is the higher the device

logic/routing utilization, the lower the compression ratio (where the compression

ratio is defined as the original bitstream size divided by the compressed bitstream

size).

For Stratix designs, based on a suite of designs with varying amounts of logic

utilization, the minimum compression ratio was observed to be 1.9 or a ~47% size

reduction for these designs. Table 1–6 lists sample compression ratios from a suite of

Stratix designs. These numbers serve as a guideline (not a specification) to help you

allocate sufficient configuration memory to store compressed bitstreams.

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