2

Functional Diagram

GND = 8

6

7

5

4

14

13

12

11

THREE-

OUTPUT

8-BIT

STORAGE

REGISTER

8-STAGE

SHIFT

REGISTER

OE

15

1

3

2

10

9

DATA

CP

STROBE

STATE

TRUTH TABLE

INPUTS

PARALLEL OUTPUTS

SERIAL OUTPUTS

CP

OE

STR

D

↑

L

X

X

Z

Z

Q’6

NC

↓

LX

X

Z

Z

NC

↑

H

L

X

NC

NC

Q’6

NC

↑

HH

L

L

Q’6

NC

↑

H

HHH

Q’6

NC

↓

H

H

H

NCNCNC

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, NC = No charge, Z = High Impedance Off-state,

↑ = Transition from Low to High Level, ↓ = Transition from High to Low.

NOTE:

1. At the positive clock edge the information in the seventh register stage is transferred to the 8th register stage and QS1 output.

CD54HC4094, CD74HC4094, CD74HCT4094