DAC5682Z datasheet(39/59 Pages) TI

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DCLKP

D0P

D0N

D15P

D15N

DCLKN

LVDS

FPGA

DAC

500MHz

(½ Rate)

1000MSPS DDR

(2 bits/CLKIN cycle)

1000MHz

250MHz

DCLK

Delay Lock Loop

LVDS

4b SERDES

(bit 0)

4b SERDES

(CLKOUT)

4b SERDES

(bit 15)

1,0,1,0...

SYNCP

SYNCN

LVDS

4b SERDES

(SYNC)

Ref CLK

Gen &

Sync

250MHz

÷1

System

SYNC

4x Clock

Multiplier PLL

D15P/N

SERDES

S2[15]

S3[15]

S4[15]

S1[0]

S2[0]

S3[0]

S4[0]

Sample “S1”

Sample “S2”

Sample “S3”

Sample “S4”

S1[15]

S1[15:0]

S2[15:0]

S3[15:0]

S4[15:0]

250 MHz (FPGA)

1000 MHz (FPGA)

CLKB

(500MHz)

To DAC

250MHz

Clock

DCLKP/N

500 MHz

CLKB (DAC)

Bit 15 Data Nibble

Bit 0 Data Nibble

Repeating 4 bit

Sequence “1010” …

Normally = “1111”

Ocassional = “1101”

for SYNC event

DDR Clock Gen

SYNC Generator

Using common “data driven”

SERDES blocks, relative

delays from CLK, SYNC and

DATA are matched. (200pS)

DCLK Data Nibble

SYNC Data Nibble

500 MHz

CLKA (DAC)

CLKA

(500MHz)

DLL Phase Offset control

determines CLKA/B skew.

D0P/N

SERDES

SYNCP/N

SERDES

CLKA F

CLKB F

500 MHz

CLKIN to DLL

SYNC input combines TXENABLE

function (normally “1”) and SYNChronizer

function (“0” to “1” transition)

LVDS Inputs

D[15:0]P,

SYNCP

D[15:0]N,

SYNCN

LVDS

Receiver

100 pF

Total

To Adjacent

LVDS Input

To Adjacent

LVDS Input

Ref Note (1)

Note (1): RCENTER node common

to all D[15:0]P/N and SYNCP/N

receiver inputs

DAC5682Z

www.ti.com ........................................................................................................................................................ SLLS853C – AUGUST 2007 – REVISED JUNE 2009

Figure 39. Example FPGA-Based LVDS Data Flow to DAC

The D[15:0]P/N and SYNCP/N LVDS pairs have the input configuration shown in Figure 40. Figure 41 shows the

typical input levels and common-mode voltage used to drive these inputs.

Figure 40. D[15:0]P/N and SYNCP/N LVDS Input Configuration

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