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ADS58C48IPFP датащи(PDF) 16 Page - Texas Instruments

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номер детали ADS58C48IPFP
подробное описание детали  Quad Channel IF Receiver with SNRBoost 3G
PDF  70 Pages
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производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
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ADS58C48IPFP датащи(HTML) 16 Page - Texas Instruments

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ADS58C48
SLAS689 – MAY 2010
www.ti.com
SERIAL REGISTER MAP
Table 7. Summary of Functions Supported by Serial Interface(1) (2)
REGISTER
REGISTER DATA
ADDRESS
A7–A0 IN
D7
D6
D5
D4
D3
D2
D1
D0
HEX
00
0
0
0
0
0
0
<RESET>
<READOUT>
01
<LVDS SWING>
0
0
25
<GAIN CH B>
0
<TEST PATTERNS – CH B>
26
0
<CH B SNRBoost FILTER #>
<SNRBoost
28
0
0
0
0
0
0
0
CH B ON>
<DATA FORMAT CH A CH
29
0
0
0
0
0
0
B>
2B
<GAIN CH A>
0
<TEST PATTERNS – CH A>
2D
0
<CH A SNRBoost FILTER #>
<SNRBoost
2E
0
0
0
0
0
0
0
CH A ON>
31
<GAIN CH C>
0
<TEST PATTERNS – CH C>
32
0
<CH C SNRBoost FILTER #>
<SNRBoost
34
0
0
0
0
0
0
0
CH C ON>
<DATA FORMAT CH C CH
35
0
0
0
0
0
0
D>
37
<GAIN CH D>
0
<TEST PATTERNS – CH D>
39
0
<CH D SNRBoost FILTER #>
<SNRBoost
3A
0
0
0
0
0
0
0
CH D ON>
<EN OFFSET
3D
0
0
0
0
0
0
0
CORR>
3F
0
0
<CUSTOM PATTERN HIGH D10:D5>
40
<CUSTOM PATTERN D4:D0>
0
0
0
<CMOS CLKOUT
41
<LVDS CMOS>
0
0
<PDN OBUF LVDS>
STRENGTH>
<DIGITAL
42
<CLKOUT FALL POSN>
<CLKOUT RISE POSN>
<PDN OBUF CMOS>
0
MODE 1>
DIGITAL
44
0
0
0
0
0
0
0
MODE 2>
<LVDS
<LVDS
<PDN
<CONFIG
45
<STBY>
CLKOUT
DATA
0
0
0
GLOBAL>
PDN Pin>
STRENGTH> STRENGTH>
BF
<OFFSET PEDESTAL – CH B>
0
0
0
0
0
C1
<OFFSET PEDESTAL – CH A>
0
0
0
0
0
C3
<OFFSET PEDESTAL – CH C>
0
0
0
0
0
C5
<OFFSET PEDESTAL – CH D>
0
0
0
0
0
<FREEZE
CF
OFFSET
0
<OFFSET CORR TIME CONSTANT>
0
0
CORR>
<OVERRIDE
EA
0
0
0
0
0
0
0
SNRB pins>
F1
0
0
0
0
0
0
<EN LVDS SWING>
03
0
0
0
0
0
0
<HIGH PERF MODE>
(1)
All registers default to zeros after reset.
(2)
Multiple functions in a register can be programmed in a single write operation.
16
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s) :ADS58C48



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