DSP56F805 datasheet(13/56 Pages) FREESCALE

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Interrupt and Program Control Signals

56F805 Technical Data, Rev. 16

Freescale Semiconductor

2.5 Interrupt and Program Control Signals

Table 2-9 Interrupt and Program Control Signals

No. of

Pins

Signal

Name

Signal

Type

State

During

Reset

Signal Description

IRQA

Input

(Schmitt)

Input

External Interrupt Request A—The IRQA input is a synchronized

external interrupt request indicating an external device is requesting

service. It can be programmed to be level-sensitive or

negative-edge-triggered.

IRQB

Input

(Schmitt)

Input

External Interrupt Request B—The IRQB input is an external

interrupt request indicating an external device is requesting service.

It can be programmed to be level-sensitive or

negative-edge-triggered.

RESET

Input

(Schmitt)

Input

Reset—This input is a direct hardware reset on the processor.

When RESET is asserted low, the device is initialized and placed in

the Reset state. A Schmitt trigger input is used for noise immunity.

When the RESET pin is deasserted, the initial chip operating mode

is latched from the EXTBOOT pin. The internal reset signal will be

deasserted synchronous with the internal clocks, after a fixed

number of internal clocks.

To ensure complete hardware reset, RESET and TRST should be

asserted together. The only exception occurs in a debugging

environment when a hardware device reset is required and it is

necessary not to reset the OnCE/JTAG module. In this case, assert

RESET, but do not assert TRST.

RSTO

Output

Reset Output—This output reflects the internal reset state of the

chip.

EXTBOOT

Input

(Schmitt)

Input

External Boot—This input is tied to VDD to force device to boot

from off-chip memory. Otherwise, it is tied to VSS.

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