CS51312 datasheet(13/22 Pages) ONSEMI

13 / 22 page

CS51312

http://onsemi.com

Figure 13. Adaptive FET Non−Overlap (100 ns/div)

Channel 1 − GATE(H) (5.0 V/div)

Channel 2 − GATE(L) (5.0 V/div)

Channel 3 − Inductor Switching Node (10 V/div)

CS51312−BASED VCC(CORE) BUCK REGULATOR

DESIGN EXAMPLE

Step 1: Definition of the Design Specifications

The output voltage tolerance can be affected by any or all

of the following reasons:

1. buck regulator output voltage setpoint accuracy;

2. output voltage change due to discharging or charging

of the bulk decoupling capacitors during a load

current transient;

3. output voltage change due to the ESR and ESL of the

bulk and high frequency decoupling capacitors,

circuit traces, and vias;

4. output voltage ripple and noise.

Budgeting the tolerance is left up to the designer who must

take into account all of the above effects and provide an

output voltage that will meet the specified tolerance at the

load.

The designer must also ensure that the regulator

component temperatures are kept within the manufacturer’s

specified ratings at full load and maximum ambient

temperature..

Step 2: Selection of the Output Capacitors

These components must be selected and placed carefully

to yield optimal results. Capacitors should be chosen to

provide acceptable ripple on the regulator output voltage.

Key specifications for output capacitors are their ESR

(Equivalent Series Resistance), and ESL (Equivalent Series

Inductance). For best transient response, a combination of

low value/high frequency and bulk capacitors placed close

to the load will be required.

In order to determine the number of output capacitors the

maximum voltage transient allowed during load transitions

has to be specified. The output capacitors must hold the

output voltage within these limits since the inductor current

can not change with the required slew rate. The output

capacitors must therefore have a very low ESL and ESR.

The voltage change during the load current transient is:

DVOUT + DIOUT

ESL

Dt )

ESR ) tTR

COUT

where:

ΔIOUT / Δt = load current slew rate;

ΔIOUT = load transient;

Δt = load transient duration time;

ESL = Maximum allowable ESL including capacitors,

circuit traces, and vias;

ESR = Maximum allowable ESR including capacitors and

circuit traces;

tTR = output voltage transient response time.

The designer has to independently assign values for the

change in output voltage due to ESR, ESL, and output

capacitor discharging or charging. Empirical data indicates

that most of the output voltage change (droop or spike

depending on the load current transition) results from the

total output capacitor ESR.

The maximum allowable ESR can then be determined

according to the formula

ESRMAX + D

VESR

DIOUT

where ΔVESR = change in output voltage due to ESR

(assigned by the designer).

Once the maximum allowable ESR is determined, the

number of output capacitors can be found by using the

formula

Number of capacitors +

ESRCAP

ESRMAX

where:

ESRCAP = maximum ESR per capacitor (specified in

manufacturer’s data sheet);

ESRMAX = maximum allowable ESR.

The actual output voltage deviation due to ESR can then

be verified and compared to the value assigned by the

designer:

DVESR + DIOUT

ESRMAX

Similarly, the maximum allowable ESL is calculated from

the following formula:

ESLMAX + D

VESL

where:

ΔI/ΔT = load current slew rate (as high as 20 A/μs);

ΔVESL = change in output voltage due to ESL.

The actual maximum allowable ESL can be determined

by using the equation:

ESLMAX +

ESLCAP

Number of output capacitors

where ESLCAP = maximum ESL per capacitor (it is

estimated that a 10 × 12 mm Aluminum Electrolytic

capacitor has approximately 4.0 nH of package inductance).

The actual output voltage deviation due to the actual

maximum ESL can then be verified:

CS51312 датащи(PDF) 13 Page - ON Semiconductor

CS51312 датащи(HTML) 13 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

датащи скачать

ссылки URL