3

2570L–AVR–08/07

ATmega325/3250/645/6450

Figure 1-2.

Pinout ATmega325/645

Note:

The large center pad underneath the QFN/MLF packages is made of metal and internally con-

nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If

the center pad is left unconnected, the package might loosen from the board.

2.

Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of

other AVR microcontrollers manufactured on the same process technology. Min and Max values

will be available after the device is characterized.

3.

Overview

The ATmega325/3250/645/6450 is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the

ATmega325/3250/645/6450 achieves throughputs approaching 1 MIPS per MHz allowing the

system designer to optimize power consumption versus processing speed.

PC0

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1B/PCINT14) PB6

(OC1A/PCINT13) PB5

PC1

PG0

PC2

PC3

PC4

PC5

PC6

PC7

PA7

PG2

PA6

PA5

PA4

PA3

PG1

INDEX CORNER

(SS/PCINT8) PB0

2

3

1

4

5

6

7

8

9

10

11

12

13

14

16

15

47

46

48

45

44

43

42

41

40

39

38

37

36

35

33

34

ATmega325/645

DNC