CAT1232LP, CAT1832

Doc. No. MD-3018 Rev. F

6

© 2009 SCILLC. All rights reserved.

Characteristics subject to change without notice

WATCHDOG TIMER AND ST

¯¯ INPUT

A watchdog timer stops and restarts a microprocessor

that has stopped proper operation or become “hung”.

The watchdog performs this function by monitoring the

ST

¯¯ input. After the reset outputs go inactive the ST

¯¯

input must be strobed with a high-to-low signal

transition prior to the minimum watchdog timeout

period. However if the ST

¯¯ input is not strobed with a

high-to-low signal transition prior to a watchdog

timeout the reset outputs will become active for TRST

reseting and restarting the microprocessor. Once the

resets return to the inactive state the watchdog timer

restarts the process.

The TD input allows the user to select from three

predetermined watchdog timeout periods. Always use

the minimum timeout period to determine the required

frequency of ST

¯¯ high-to-low transitions and the

maximum to determine the time prior to the reset

outputs becoming active. ST

¯¯ pulse widths must be

20 ns or greater.

The watchdog timer cannot be disabled. It must be

strobed with a high-to-low signal transition to avoid a

watchdog timeout and subsequent reset.

Watchdog Time-out Period (ms)

TD Voltage

Level

Min

Nominal

Max

GND

62.5

150

250

Floating

250

600

1000

500

1200

2000

Figure 4. CAT1832 Application Circuit:

Pushbutton Reset

Figure 5. CAT1232LP Application Circuit: Watchdog Timer

Figure 6. Timing Diagram: Pushbutton Reset

Figure 7. Timing Diagram: Strobe Input

PBRST

3.3V

1

VCC

TD

2

ST

TOL

CAT1832

µP

3

4

RESET

GND

8

7

6

5

RESET

RESET

I/O

PBRST

5V

1

VCC

TD

2

ST

TOL

CAT1232LP

µP

Decoder

3

4

RESET

GND

8

7

6

5

RESET

MREQ

Address Bus

RESET

RESET

RESET

PBRST

RESET

RESET

ST

Valid

Strobe

Valid

Strobe

Invalid

Strobe

(Min)

(Min)

Note: ST is ignored whenever a reset is active