CAT1024 datasheet(13/20 Pages) ONSEMI

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CAT1024, CAT1025

Doc. No. MD-3008 Rev. R

Characteristics subject to change without notice

Immediate/Current Address Read

The CAT1024 and CAT1025 address counter

contains the address of the last byte accessed,

incremented by one. In other words, if the last READ

or WRITE access was to address N, the READ

immediately following would access data from

address N + 1. For N = E = 255, the counter will

wrap around to zero and continue to clock out valid

data. After the CAT1024/1025 receives its slave

address information (with the R/W

¯¯ bit set to one), it

issues an acknowledge, then transmits the 8-bit byte

requested. The master device does not send an

acknowledge, but will generate a STOP condition.

Selective/Random Read

Selective/Random READ operations allow the

Master device to select at random any memory

location for a READ operation. The Master device

first performs a ‘dummy’ write operation by sending

the START condition, slave address and byte

addresses of the location it wishes to read. After the

CAT1024 and CAT1025 acknowledges, the Master

device sends the START condition and the slave

address again, this time with the R/W

¯¯ bit set to one.

The CAT1024 and CAT1025 then responds with its

acknowledge and sends the 8-bit byte requested.

The master device does not send an acknowledge

but will generate a STOP condition.

Sequential Read

The Sequential READ operation can be initiated by

either the Immediate Address READ or Selective READ

operations. After the CAT1024 and CAT1025 sends the

inital 8-bit byte requested, the Master will responds with

an acknowledge which tells the device it requires more

data. The CAT1024 and CAT1025 will continue to

output an 8-bit byte for each acknowledge, thus sending

the STOP condition.

The data being transmitted from the CAT1024 and

CAT1025 is sent sequentially with the data from

address N followed by data from address N + 1. The

READ operation address counter increments all of the

CAT1024 and CAT1025 address bits so that the entire

memory array can be read during one operation.

Figure 11. Selective Read Timing

Figure 12. Sequential Read Timing

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SDA LINE

BYTE

ADDRESS (n)

DATA n

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SDA LINE

DATA n+x

DATA n

DATA n+1

DATA n+2

SLAVE

ADDRESS

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