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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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68HC05P9A датащи(PDF) 49 Page - Freescale Semiconductor, Inc |
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68HC05P9A датащи(HTML) 49 Page - Freescale Semiconductor, Inc |
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49 / 90 page  GENERAL RELEASE SPECIFICATION TIMER Rev. 2.0 8-5 8.4 Timer Control Register (TCR) $12 The TCR is a read/write register containing five control bits. Three bits control interrupts associated with the timer status register flags ICF, OCF, and TOF. ICIE — Input Capture Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled OCIE — Output Compare Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled TOIE — Timer Overflow Interrupt Enable 1 = Interrupt enabled 0 = Interrupt disabled IEDG — Input Edge Value of input edge determines which level transition on TCAP pin will trigger free-running counter transfer to the input capture register 1 = Positive edge 0 = Negative edge Reset does not affect the IEDG bit (U=unaffected). OLVL — Output Level Value of output level is clocked into output level register by the next successful output compare and will appear on the TCMP pin 1 = High output 0 = Low output Bits 2, 3, and 4 — Not used Always read zero $12 ICIE OCIE TOIE 0 0 0 IEDG OLVL RESET: 00000000 Figure 8-2. Timer Control Register Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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