ADT7467ARQZ-R7 datasheet(64/77 Pages) ONSEMI

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ADT7467

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Table 24. Register 0x37—Dynamic TMIN Control Register 2 (Power-On Default = 0x00)1

Bit

Name

R/W

Description

<2:0>

CYR1

Read/write

3-bit Remote 1 cycle value. These three bits define the delay time, in terms of the number of monitoring

cycles, for making subsequent TMIN adjustments in the control loop for the Remote 1 channel. The system is

associated with thermal time constants that must be found to optimize the response of the fans and the

control loop.

Bits

Decrease (Short) Cycle

Increase (Long) Cycle

000

8 cycles (1 sec)

16 cycles (2 sec)

001

16 cycles (2 sec)

32 cycles (4 sec)

010

32 cycles (4 sec)

64 cycles (8 sec)

011

64 cycles (8 sec)

128 cycles (16 sec)

100

128 cycles (16 sec)

256 cycles (32 sec)

101

256 cycles (32 sec)

512 cycles (64 sec)

110

512 cycles (64 sec)

1024 cycles (128 sec)

111

1024 cycles (128 sec)

2048 cycles (256 sec)

<5:3>

CYL

Read/write

3-bit local temperature cycle value. These three bits define the delay time, in terms of number of monitoring

cycles, for making subsequent TMIN adjustments in the control loop for the local temperature channel. The

system is associated with thermal time constants that must be found to optimize the response of the fans

and the control loop.

Bits

Decrease (Short) Cycle

Increase (Long) Cycle

000

8 cycles (1 sec)

16 cycles (2 sec)

001

16 cycles (2 sec)

32 cycles (4 sec)

010

32 cycles (4 sec)

64 cycles (8 sec)

011

64 cycles (8 sec)

128 cycles (16 sec)

100

128 cycles (16 sec)

256 cycles (32 sec)

101

256 cycles (32 sec)

512 cycles (64 sec)

110

512 cycles (64 sec)

1024 cycles (128 sec)

111

1024 cycles (128 sec)

2048 cycles (256 sec)

<7:6>

CYR2

Read/write

2 LSBs of 3-bit Remote 2 cycle value. The MSB of the 3-bit code resides in dynamic TMIN Control Register 1

(0x36). These three bits define the delay time, in terms of number of monitoring cycles, for making

subsequent TMIN adjustments in the control loop for the Remote 2 channel. The system is associated with

thermal time constants that must be found to optimize the response of fans and the control loop.

Bits

Decrease Cycle

Increase Cycle

000

8 cycles (1 sec)

16 cycles (2 sec)

001

16 cycles (2 sec)

32 cycles (4 sec)

010

32 cycles (4 sec)

64 cycles (8 sec)

011

64 cycles (8 sec)

128 cycles (16 sec)

100

128 cycles (16 sec)

256 cycles (32 sec)

101

256 cycles (32 sec)

512 cycles (64 sec)

110

512 cycles (64 sec)

1024 cycles (128 sec)

111

1024 cycles (128 sec)

2048 cycles (256 sec)

1 This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this register fail.

Table 25. Maximum PWM Duty Cycle Registers (Power-On Default = 0xFF)1

R/W

Description

0x38

Read/write

Maximum duty cycle for PWM1 output, default = 100% (0xFF).

0x39

Read/write

Maximum duty cycle for PWM2 output, default = 100% (0xFF).

0x3A

Read/write

Maximum duty cycle for PWM3 output, default = 100% (0xFF).

1 These registers set the maximum PWM duty cycle of the PWM output.

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