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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AT90USB82 датащи(PDF) 37 Page - ATMEL Corporation |
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AT90USB82 датащи(HTML) 37 Page - ATMEL Corporation |
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37 / 306 page  37 7707E–AVR–11/08 AT90USB82/162 Figure 6-6. PLL Clocking System 6.9.2 PLL Control and Status Register – PLLCSR • Bit 7..5 – Res: Reserved Bits These bits are reserved bits in the AT90USB82/162 and always read as zero. • Bit 4..2 – PLLP2:0 PLL prescaler These bits allow to configure the PLL input prescaler to generate the 8MHz input clock for the PLL. • Bit 1 – PLLE: PLL Enable When the PLLE is set, the PLL is started and if needed internal RC Oscillator is started as a PLL reference clock. If PLL is selected as a system clock source the value for this bit is always 1. XTAL2 XTAL1 XTAL PLL 6x PLLE Lock Detector PLOCK clkUSB (48MHz) PLL clock Prescaler System Clock clk 8MHz Ext. Int RC 8MHz. Clock Switch Clock Mux (fuse) Bit 7 65 4321 0 $29 ($29) PLLP2 PLLP1 PLLP0 PLLE PLOCK PLLCSR Read/Write R R R R R R R/W R Initial Value 0 0 0 0 0 0 0/1 0 Table 6-10. PLL input prescaler configurations PLLP2 PLLP1 PLLP0 Clock Division Factor 00 0 1 00 1 2 0 1 0 Reserved 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved |
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