V

CC

V

POR

V

PORF

Time

POR

Time

PCA9534A

www.ti.com

SCPS141F – SEPTEMBER 2006 – REVISED JUNE 2010

Interrupt Requirements

The expected performance of the interrupt feature is that INT is to be cleared (de-asserted) when the input

register is read or all inputs return to the last read values. INT is also de-asserted when both of the following

occur:

•

the device was a read of the input register, but the command byte may have been written with 00h without

ever going on to read the Input register.

•

when reading any other valid device on the bus.

the command byte to something other than 00 (hex) after a read operation to the device.

Copyright © 2006–2010, Texas Instruments Incorporated

Submit Documentation Feedback

25

Product Folder Link(s): PCA9534A