LM3404 datasheet(2/6 Pages) NSC

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Test PCB

The test PCB for this application note is the LM3402/04

PSOP-8 Evaluation board. The board measures 1.95” by

1.25”, with 2 layers of 1oz copper and 62mil FR4. To obtain

best thermal performance, most of the top layer and the entire

bottom layer are composed of large copper areas (shapes).

These areas act as heatsinks for the LM3404HV. Of special

importance is the pad and thermal via arrangement that con-

nects the DAP of the PSOP-8 package to the ground plane

on the bottom layer. Figure 2 shows a detail of the pad, which

is the recommended layout for best thermal performance. The

LM3404HV in PSOP-8 can be used on a standard SO-8 foot-

print, and the LM3404HV in SO-8 can be used on the PSOP-8

Evaluation Board, however neither of these options take ad-

vantage of the enhanced thermal performance of the PSOP-8

when properly soldered to a thermal pad connected to a large

(1 square inch or more) copper area. Plots of the PCB layers

are shown at the end of this document.

30019202

FIGURE 2. PSOP-8 Pad and Thermal Via Layout

Power Dissipation

Power dissipation inside the LM3404HV can be divided into

three types: conduction (I2R) loss, gate charge loss, and

switching loss. For each calculation the maximum, worst-

case values have been used. Duty cycle, D, is 0.75. The

MOSFET R

DSON is 0.75Ω, gate charge, QG is 6 nC, and the

rise are fall times, t

R and tF, are 20 ns each.

Conduction loss, P

C, in the internal MOSFET

C = (IF x D)

2 x R

DSON = (1.0 x 0.75)

2 x 0.75 = 420 mW

Gate charging and VCC loss, P

G, in the gate drive and linear

regulator:

G = (IIN-OP + fSW x QG) x VIN

G = (675 x 10

-6 + 550000 x 6 x 10-9) x 48 = 191 mW

Switching loss, P

S, in the internal NFET:

S = 0.5 x VIN x IF x (tR + tF) x fSW

S = 0.5 x 48 x 1.0 x (40 x 10

-9) x 550000 = 528 mW

The total power dissipation inside the LM3404HV is then:

D = PC + PG + PS = 1.14W

Thermal Calculations

The LM3404HV has a maximum operating junction tempera-

ture (T

J) of 125°C. Calibrated testing of the LM3404HV in both

the SO-8 package (NSID LM3404HVMA) and PSOP-8 (NSID

LM3404HVMR) was performed using the actual PSOP-8

evaluation PCB. The results for junction-to-ambient thermal

resistance (

JA) in °C/W are summarized below:

Package

0.5W

1.0W

1.5W

SO-8

102

N/A

PSOP-8

50.9

49.6

48.4

To match the expected application conditions, all tests were

performed with no air flow. Data for the SO-8 package at 1.5W

is not available because the final T

J exceeded 125°C. θJA is

as much a property of the PCB as it is of the semiconductor

chip. The top layer of the PSOP-8 Evaluation board is ap-

proximately 75% copper, and the bottom (accounting for

holes and traces) is approximately 90%. The estimated total

copper area is therefore (0.75 + 0.9) x (1.25” x 1.95”) = 4

square inches.

With the power dissipation and thermal resistance data the

maximum ambient operating temperature can be predicted

or, given the ambient operating temperature, a decision can

be made as to the proper package for the LM3404HV.

Maximum ambient operating temperature, T

A-MAX, can be de-

termined with the following equation:

A-MAX = TJ-MAX – PD x θJA

A-MAX (SO-8) = 125 – 1.14 x 99 = 12°C

A-MAX (PSOP-8) = 125 – 1.14 x 50 = 68°C

It is clear from the calculations that the PSOP-8 package must

be used in this high dissipation application.

As an alternative, if the ambient temperature is known, then

the die temperature of the LM3404HV can be predicted by re-

arranging the previous equation:

J = TA + PD x θJA

For example, if the ambient temperature inside an enclosure

with high power LEDs reaches 60°C, then the two package

options can again be evaluated:

J (SO-8) = 60 + 1.14 x 99 = 173°C

J (PSOP-8) = 60 + 1.14 x 50 = 117°C

Again, the results show that the SO-8 package will not be able

to keep the junction temperature within specification limits.

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