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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC16F датащи(PDF) 32 Page - Microchip Technology |
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PIC16F датащи(HTML) 32 Page - Microchip Technology |
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32 / 40 page  PIC16F/LF182X/PIC12F/LF1822 DS41390C-page 32 Advance Information 2010 Microchip Technology Inc. 8.0 ELECTRICAL SPECIFICATIONS Refer to device specific data sheet for absolute maximum ratings. TABLE 8-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE AC/DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +85°C Sym. Characteristics Min. Typ. Max. Units Conditions/Comments Supply Voltages and Currents VDD VDD Read/Write and Row Erase operations PIC12F1822 PIC16F182X 2.1 — 5.5 V PIC12LF1822 PIC16LF182X 2.1 — 3.6 V Bulk Erase operations PIC12F1822 PIC16F182X 2.7 — 5.5 V PIC12LF1822 PIC16LF182X 2.7 — 3.6 V IDDI Current on VDD, Idle — — 1.0 mA IDDP Current on VDD, Programming — — 3.0 mA IPP VPP Current on MCLR/VPP — — 600 A VIHH High voltage on MCLR/VPP for Program/Verify mode entry 8.0 — 9.0 V TVHHR MCLR rise time (VIL to VIHH) for Program/Verify mode entry —— 1.0 s I/O pins VIH (ICSPCLK, ICSPDAT, MCLR/VPP) input high level 0.8 VDD —— V VIL (ICSPCLK, ICSPDAT, MCLR/VPP) input low level — — 0.2 VDD V VOH ICSPDAT output high level VDD-0.7 VDD-0.7 VDD-0.7 —— V IOH = 3.5 mA, VDD = 5V IOH = 3 mA, VDD = 3.3V IOH = 2 mA, VDD = 1.8V VOL ICSPDAT output low level —— VSS+0.6 VSS+0.6 VSS+0.6 V IOH = 8 mA, VDD = 5V IOH = 6 mA, VDD = 3.3V IOH = 3 mA, VDD = 1.8V Programming Mode Entry and Exit TENTS Programing mode entry setup time: ICSPCLK, ICSPDAT setup time before VDD or MCLR 100 — — ns TENTH Programing mode entry hold time: ICSPCLK, ICSPDAT hold time after VDD or MCLR 250 — — s Serial Program/Verify TCKL Clock Low Pulse Width 100 — — ns TCKH Clock High Pulse Width 100 — — ns TDS Data in setup time before clock 100 — — ns TDH Data in hold time after clock 100 — — ns TCO Clock to data out valid (during a Read Data command) 0 — 80 ns TLZD Clock to data low-impedance (during a Read Data command) 0 — 80 ns THZD Clock to data high-impedance (during a Read Data command) 0 — 80 ns TDLY Data input not driven to next clock input (delay required between command/data or command/command) 1.0 — — s TERAB Bulk Erase cycle time — — 5 ms TERAR Row Erase cycle time — — 2.5 ms |
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