LTM2882 datasheet(13/18 Pages) LINER

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LTM2882

2882fa

APPLICATIONS INFORMATION

PCB Layout

The high integration of the LTM2882 makes PCB layout

very simple. However, to optimize its electrical isolation

characteristics, EMI, and thermal performance, some

layout considerations are necessary.

• Under heavily loaded conditions, VCC and GND current

can exceed 300mA. Use sufﬁcient copper on the PCB to

ensure resistive losses do not cause the supply voltage

to drop below the minimum allowed level. Similarly,

size the VCC2 and GND2 conductors to support any

external load current. These heavy copper traces will

also help to reduce thermal stress and improve the

thermal conductivity.

• Input and Output decoupling is not required, since

these components are integrated within the package.

If an additional bulk capacitor is used a value of 6.8μF

to 22μF is recommended. The recommendation for

EMI sensitive applications is to include an additional

low ESL ceramic capacitor of 1μF to 4.7μF, placed close

to the power and ground terminals. Alternatively, use a

number of smaller value parallel capacitors to reduce

ESL and achieve the same net capacitance.

• Do not place copper on the PCB between the inner col-

umns of pads. This area must remain open to withstand

the rated isolation voltage. Slot the PCB in this area to

facilitate cleaning and ensure contamination does not

compromise the isolation voltage.

• The use of solid ground planes for GND and GND2

is recommended for non-EMI critical applications to

optimize signal ﬁdelity, thermal performance, and to

minimize RF emissions due to uncoupled PCB trace

conduction. The drawback of using ground planes,

where EMI is of concern, is the creation of a dipole

antenna structure, which can radiate differential voltages

formed between GND and GND2. If ground planes are

used, minimize their area, and use contiguous planes,

any openings or splits can increase RF emissions.

• For large ground planes a small capacitance (≤ 330pF)

from GND to GND2, either discrete or embedded within

the substrate, provides a low impedance current return

path for the module parasitic capacitance, minimizing

any high frequency differential voltages and substantially

reducing radiated emissions. Discrete capacitance is not

as effective due to parasitic ESL; in addition consider

voltage rating, leakage, and clearance for component

selection. Embedding the capacitance within the PCB

substrate provides a near ideal capacitor and eliminates

the other component selection issues, however the PCB

must be 4 layers and the use of a slot is not compatible.

Exercise care in applying either technique to ensure the

voltage rating of the barrier is not compromised.

The PCB layout in Figure 7 shows a recommended con-

ﬁguration for a low EMI RS232 application.

Figure 7. Recommended PCB Layout

T1OUT

DE = VCC2

R1IN

T2OUT

R2IN

GND2

T1IN

R1OUT

VCC = VL

= ON

= DIN

T2IN

R2OUT

GND

2882 F07

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