www.ti.com

LVDS OUTPUT TIMING CHARACTERISTICS

(1) (2)

LVDS OUTPUT TIMING CHARACTERISTICS

(1) (2)

ADS5281

ADS5282

SBAS397H – DECEMBER 2006 – REVISED MARCH 2008

Typical values are at +25

°C, minimum and maximum values are measured across the specified temperature range of T

+85

°C, sampling frequency = as specified, C

noted.

ADS528x

40MSPS

50MSPS

65MSPS

PARAMETER

TEST CONDITIONS

(5)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

Data valid

Data setup time

(6)

0.67

0.47

0.27

ns

Data hold time

(6)

0.85

0.65

0.4

ns

becoming invalid

(7)

Input clock (ADCLK) rising edge

Clock propagation delay

10

14

16.6

10

12.5

14.1

9.7

11.5

14

ns

rising edge cross-over

Duty cycle of differential clock,

LVDS bit clock duty cycle

45.5

50

53

45

50

53.5

41

50

57

Bit clock cycle-to-cycle

250

250

250

ps, pp

jitter

Frame clock cycle-to-cycle

150

150

150

ps, pp

jitter

Data rise time, data fall

Rise time is from –100mV to +100mV

0.09

0.2

0.4

0.09

0.2

0.4

0.09

0.2

0.4

ns

time

Fall time is from +100mV to –100mV

Output clock rise time,

Rise time is from –100mV to +100mV

0.09

0.2

0.4

0.09

0.2

0.4

0.09

0.2

0.4

ns

output clock fall time

Fall time is from +100mV to –100mV

(1)

All characteristics are at the maximum rated speed for each speed grade.

(2)

Timing parameters are ensured by design and characterization; not production tested.

(3)

(4)

(5)

Measurements are done with a transmission line of 100

Ω characteristic impedance between the device and the load.

(6)

Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume

that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as

reduced timing margin.

(7)

Data valid refers to a logic high of +100mV and a logic low of –100mV.

Typical values are at +25

°C, minimum and maximum values are measured across the specified temperature range of T

+85

°C, sampling frequency = as specified, C

noted.

ADS528x

30MSPS

20MSPS

10MSPS

PARAMETER

TEST CONDITIONS

(5)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

Data valid

Data setup time

(6)

0.8

1.5

3.7

ns

Data hold time

(6)

1.2

1.9

3.9

ns

becoming invalid

(7)

Input clock (ADCLK) rising edge

Clock propagation delay

9.5

13.5

17.3

9.5

14.5

17.3

10

14.7

17.1

ns

rising edge cross-over

Duty cycle of differential clock,

LVDS bit clock duty cycle

46.5

50

52

48

50

51

49

50

51

Bit clock cycle-to-cycle

250

250

750

ps, pp

jitter

Frame clock cycle-to-cycle

150

150

500

ps, pp

jitter

Data rise time, data fall

Rise time is from –100mV to +100mV

0.09

0.2

0.4

0.09

0.2

0.4

0.09

0.2

0.4

ns

time

Fall time is from +100mV to –100mV

Output clock rise time,

Rise time is from –100mV to +100mV

0.09

0.2

0.4

0.09

0.2

0.4

0.09

0.2

0.4

ns

output clock fall time

Fall time is from +100mV to –100mV

(1)

All characteristics are at the speeds other than the maximum rated speed for each speed grade.

(2)

Timing parameters are ensured by design and characterization; not production tested.

(3)

(4)

(5)

Measurements are done with a transmission line of 100

Ω characteristic impedance between the device and the load.

(6)

Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume

that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as

reduced timing margin.

(7)

Data valid refers to a logic high of +100mV and a logic low of –100mV.

Copyright © 2006–2008, Texas Instruments Incorporated

Submit Documentation Feedback

13

Product Folder Link(s): ADS5281 ADS5282