TPS54521

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SLVS981 – JUNE 2010

THERMAL INFORMATION

TPS54521

QFN

UNITS

14 PINS

47.2

32

64.8

14.4

°C/W

0.5

14.7

3.2

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

Maximum power dissipation may be limited by overcurrent protection

(3)

distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below

125°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more

information.

(4)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(5)

Test board conditions:

(a) 2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch

(b) 2 oz. copper traces located on the top of the PCB

(c) 2 oz. copper ground planes on the 2 internal layers and bottom layer

(d) 4 0.010 inch thermal vias located under the device package

(6)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(7)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(8)

(9)

(10) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Copyright © 2010, Texas Instruments Incorporated

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