Technical Note

3/9

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2010.06 - Rev.A

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BD3812F

●

Timing chart

1) Signal timing conditions

・

Data is read on the rising edge of the clock.

・

Latch is read on the falling edge of the clock.

・

Latch signal must terminate with the LOW state.

* To avoid malfunctions, clock and data signals must terminate with the LOW state.

Fig.1

Parameter

Symbol

Limits

Unit

Min.

Typ.

Max.

Minimum clock width

twc

2.0

－

－

µs

Minimum data width

twd

2.0

－

－

µs

Minimum latch width

twl

2.0

－

－

µs

LOW hold width

twh

2.0

－

－

µs

Data setup time

(DATA→CLK)

tsd

1.0

－

－

µs

Data hold time(CLK→DATA)

thd

1.0

－

－

µs

Latch setup time(CLK→LATCH)

tsl

1.0

－

－

µs

Latch hold time(DATA→LATCH)

thl

1.0

－

－

µs

Latch low setup time

ts

1.0

－

－

µs

Latch low hold time

th

1.0

－

－

µs

2) Voltage conditions for control signal

Parameter

Condition

Limits

Unit

Min.

Typ.

Max.(≦Vcc)

“H”input voltage

Vcc=5～7.3V

VEE=-5～-7.3V

2.2

－

5.5

V

“L” input voltage

0

－

1.0

V

CL

(CLOCK)

DA

DATA

LATCH

thd

thd

th

ts

tsl

thl

tsd

twc

twh

twd

twl

DATA

DATA

LATCH

90%

90%

90%

90%

10%

10%

10%

90%

90%

90%

90%

90%

10%

10%

10%

twc

Terminate

with Low.