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dsPIC30F2011 датащи(PDF) 23 Page - Microchip Technology

номер детали dsPIC30F2011
подробное описание детали  High-Performance, 16-bit Digital Signal Controllers
PDF  206 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

dsPIC30F2011 датащи(HTML) 23 Page - Microchip Technology

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© 2008 Microchip Technology Inc.
DS70139F-page 23
dsPIC30F2011/2012/3012/3013
2.4
DSP Engine
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit
adder/subtracter (with two target accumulators, round
and saturation logic).
The DSP engine also has the capability to perform
inherent
accumulator-to-accumulator
operations,
which require no additional data. These instructions are
ADD, SUB and NEG.
The dsPIC30F is a single-cycle instruction flow
architecture, therefore, concurrent operation of the
DSP engine with MCU instruction flow is not possible.
However, some MCU ALU and DSP engine resources
may be used concurrently by the same instruction
(e.g., ED, EDAC). See Table 2-2.
The DSP engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:
1.
Fractional or integer DSP multiply (IF).
2.
Signed or unsigned DSP multiply (US).
3.
Conventional or convergent rounding (RND).
4.
Automatic saturation on/off for ACCA (SATA).
5.
Automatic saturation on/off for ACCB (SATB).
6.
Automatic saturation on/off for writes to data
memory (SATDW).
7.
Accumulator
Saturation
mode
selection
(ACCSAT).
A block diagram of the DSP engine is shown in
Figure 2-2.
Note:
For CORCON layout, see Table 3-3.
TABLE 2-2:
DSP INSTRUCTION SUMMARY
Instruction
Algebraic Operation
ACC WB?
CLR
A = 0
Yes
ED
A = (x – y)2
No
EDAC
A = A + (x – y)2
No
MAC
A = A + (x * y)
Yes
MAC
A = A + x2
No
MOVSAC
No change in A
Yes
MPY
A = x * y
No
MPY.N
A = – x * y
No
MSC
A = A – x * y
Yes



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