Block Guide — S12BDM V4

5

Section 1 Introduction to Background Debug Module V4

(BDMV4)

This section describes the functionality of the Background Debug Module (BDM) sub-block of the HCS12

Core Platform.

A block diagram of the BDM is shown in Figure 1-1.

Figure 1-1 BDM Block Diagram

1.1 Overview

The Background Debug Module (BDM) sub-block is a single-wire, background debug system

implemented in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done

via the BKGD pin.

BDMV4 has enhanced capability for maintaining synchronization between the target and host while

allowing more flexibility in clock rates. This includes a sync signal to show the clock rate and a handshake

signal to indicate when an operation is complete. The system is backwards compatible with older external

interfaces.

1.2 Features

•

Single-wire communication with host development system

•

BDMV4 (and BDM2): Enhanced capability for allowing more flexibility in clock rates

•

BDMV4: SYNC command to determine communication rate

•

BDMV4: GO_UNTIL command

•

BDMV4: Hardware handshake protocol to increase the performance of the serial communication

•

Active out of reset in special single-chip mode

ENBDM

SDV

16-BIT SHIFT REGISTER

BKGD

CLOCKS

DATA

ADDRESS

HOST

SYSTEM

BUS INTERFACE

AND

CONTROL LOGIC

INSTRUCTION DECODE

AND EXECUTION

STANDARD BDM

FIRMWARE

LOOKUP TABLE

CLKSW

BDMACT

ENTAG

TRACE