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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HCS12 датащи(PDF) 139 Page - Freescale Semiconductor, Inc |
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HCS12 датащи(HTML) 139 Page - Freescale Semiconductor, Inc |
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139 / 452 page  S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor 139 Operation: If (M) • (Mask) = 0, then branch Description: Performs a bitwise logical AND of the inverse of memory location M and the mask supplied with the instruction, then branches if and only if all bits with a value of 1 in the mask byte correspond to bits with a value of one in the tested byte. Mask operands can be located at PC + 1, PC + 2, or PC + 4, depending on addressing mode. The branch offset is referenced to the next address after the relative offset (rr) which is the last byte of the instruction object code. See 3.8 Relative Addressing Mode for details of branch execution. BRSET Branch if Bits Set BRSET CCR Details: S X HIN Z V C –––––––– Source Form Address Mode(1) Object Code Access Detail HCS12 M68HC12 BRSET opr8a, msk8, rel8 BRSET opr16a, msk8, rel8 BRSET oprx0_xysp, msk8, rel8 BRSET oprx9,xysp, msk8, rel8 BRSET oprx16,xysp, msk8, rel8 DIR EXT IDX IDX1 IDX2 4E dd mm rr 1E hh ll mm rr 0E xb mm rr 0E xb ff mm rr 0E xb ee ff mm rr rPPP rfPPP rPPP rfPPP PrfPPP rPPP rfPPP rPPP rffPPP frPffPPP 1. Indirect forms of indexed addressing cannot be used with this instruction. |
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