PIC18F23K22 datasheet(48/492 Pages) MICROCHIP

48 / 492 page

PIC18(L)F2X/4XK22

DS41412B-page 48

Preliminary

 2010 Microchip Technology Inc.

3.1.3

MULTIPLE FUNCTIONS OF THE

SLEEP COMMAND

The power-managed mode that is invoked with the

SLEEP instruction is determined by the value of the

IDLEN bit at the time the instruction is executed. If

IDLEN = 0, when SLEEP is executed, the device enters

the sleep mode and all clocks stop and minimum power

is consumed. If IDLEN = 1, when SLEEP is executed,

the device enters the IDLE mode and the system clock

continues to supply a clock to the peripherals but is

disconnected from the CPU.

3.2

Run Modes

In the Run modes, clocks to both the core and

peripherals are active. The difference between these

modes is the clock source.

3.2.1

PRI_RUN MODE

The PRI_RUN mode is the normal, full-power

execution mode of the microcontroller. This is also the

default mode upon a device Reset, unless Two-Speed

Start-up is enabled (see Section 2.10 “Two-Speed

Clock Start-up Mode” for details). In this mode, the

device is operated off the oscillator defined by the

FOSC<3:0> bits of the CONFIG1H Configuration

3.2.2

SEC_RUN MODE

In SEC_RUN mode, the CPU and peripherals are

clocked from the secondary external oscillator. This

gives users the option of lower power consumption

while still using a high accuracy clock source.

SEC_RUN mode is entered by setting the SCS<1:0>

bits to ‘01’. When SEC_RUN mode is active, all of the

following are true:

• The device clock source is switched to the SOSC

oscillator (see Figure 3-1)

• The primary oscillator is shut down

• The SOSCRUN bit (OSCCON2<6>) is set

• The OSTS bit (OSCCON2<3>) is cleared

On transitions from SEC_RUN mode to PRI_RUN

mode, the peripherals and CPU continue to be clocked

from the SOSC oscillator, while the primary clock is

started. When the primary clock becomes ready, a

clock switch back to the primary clock occurs (see

Figure 3-2). When the clock switch is complete, the

SOSCRUN bit is cleared, the OSTS bit is set and the

primary clock is providing the clock. The IDLEN and

SCS bits are not affected by the wake-up and the

SOSC oscillator continues to run.

3.2.3

RC_RUN MODE

In RC_RUN mode, the CPU and peripherals are

clocked from the internal oscillator block using the

INTOSC multiplexer. In this mode, the primary clock is

shut down. When using the LFINTOSC source, this

mode provides the best power conservation of all the

Run modes, while still executing code. It works well for

user applications which are not highly timing-sensitive

or do not require high-speed clocks at all times. If the

primary clock source is the internal oscillator block –

either LFINTOSC or INTOSC (MFINTOSC or

HFINTOSC) – there are no distinguishable differences

between the PRI_RUN and RC_RUN modes during

execution. Entering or exiting RC_RUN mode,

however, causes a clock switch delay. Therefore, if the

primary clock source is the internal oscillator block,

using RC_RUN mode is not recommended.

This mode is entered by setting the SCS1 bit to ‘1’. To

maintain software compatibility with future devices, it is

recommended that the SCS0 bit also be cleared, even

though the bit is ignored. When the clock source is

switched to the INTOSC multiplexer (see Figure 3-1),

the primary oscillator is shut down and the OSTS bit is

cleared. The IRCF<2:0> bits (OSCCON<6:4>) may be

modified at any time to immediately change the clock

speed.

When the IRCF bits and the INTSRC bit are all clear,

the INTOSC output (HFINTOSC/MFINTOSC) is not

enabled and the HFIOFS and MFIOFS bits will remain

clear. There will be no indication of the current clock

source. The LFINTOSC source is providing the device

clocks.

If the IRCF bits are changed from all clear (thus,

enabling the INTOSC output) or if INTSRC or MFIOSEL

is set, then the HFIOFS or MFIOFS bit is set after the

INTOSC output becomes stable. For details, see

Table 3-2.

Clocks to the device continue while the INTOSC source

stabilizes after an interval of TIOBST.

If the IRCF bits were previously at a non-zero value, or

if INTSRC was set before setting SCS1 and the

INTOSC source was already stable, then the HFIOFS

or MFIOFS bit will remain set.

Note:

The secondary external oscillator should

already be running prior to entering

SEC_RUN mode. If the SOSCGO bit or

any of the TxSOSCEN bits are not set

when the SCS<1:0> bits are set to ‘01’,

entry to SEC_RUN mode will not occur

until SOSCGO bit is set and secondary

external oscillator is ready.

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