PIC12F1822-ISLASHMF datasheet(266/398 Pages) MICROCHIP

266 / 398 page

PIC12F/LF1822/16F/LF1823

DS41413A-page 266

Preliminary

 2010 Microchip Technology Inc.

FIGURE 24-31:

STOP CONDITION RECEIVE OR TRANSMIT MODE

24.6.10

SLEEP OPERATION

While in Sleep mode, the I2C slave module can receive

addresses or data and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if the MSSP1 interrupt is enabled).

24.6.11

EFFECTS OF A RESET

A Reset disables the MSSP1 module and terminates

the current transfer.

24.6.12

MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the

MSSP1 module is disabled. Control of the I2C bus may

be taken when the P bit of the SSP1STAT register is

set, or the bus is Idle, with both the S and P bits clear.

When the bus is busy, enabling the SSP interrupt will

generate the interrupt when the Stop condition occurs.

In multi-master operation, the SDA line must be

monitored for arbitration to see if the signal level is the

expected output level. This check is performed by

hardware with the result placed in the BCL1IF bit.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

• A Repeated Start Condition

• An Acknowledge Condition

24.6.13

MULTI -MASTER COMMUNICATION,

BUS COLLISION AND BUS

ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDA pin, arbitration takes place when the master

outputs a ‘1’ on SDA, by letting SDA float high and

another master asserts a ‘0’. When the SCL pin floats

high, data should be stable. If the expected data on

SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’,

then a bus collision has taken place. The master will set

the Bus Collision Interrupt Flag, BCL1IF, and reset the

I2C port to its Idle state (Figure 24-31).

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are deasserted and the

SSP1BUF can be written to. When the user services

the bus collision Interrupt Service Routine and if the I2C

bus is free, the user can resume communication by

asserting a Start condition.

If a Start, Repeated Start, Stop or Acknowledge condi-

tion was in progress when the bus collision occurred, the

condition is aborted, the SDA and SCL lines are deas-

serted and the respective control bits in the SSP1CON2

lision Interrupt Service Routine and if the I2C bus is free,

the user can resume communication by asserting a Start

condition.

The master will continue to monitor the SDA and SCL

pins. If a Stop condition occurs, the SSP1IF bit will be set.

A write to the SSP1BUF will start the transmission of

data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of Start and Stop conditions allows the deter-

mination of when the bus is free. Control of the I2C bus

can be taken when the P bit is set in the SSP1STAT

cleared.

SCL

SDA

SDA asserted low before rising edge of clock

Write to SSP1CON2,

set PEN

Falling edge of

SCL = 1 for TBRG, followed by SDA = 1 for TBRG

9th clock

SCL brought high after TBRG

Note: TBRG = one Baud Rate Generator period.

TBRG

after SDA sampled high. P bit (SSP1STAT<4>) is set.

TBRG

to setup Stop condition

ACK

TBRG

PEN bit (SSP1CON2<2>) is cleared by

hardware and the SSP1IF bit is set

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