MPC8308VMADDA datasheet(83/88 Pages) FREESCALE

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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 0

Freescale Semiconductor

System Design Information

These decoupling capacitors should receive their power from separate VDD, NVDD, GVDD, LVDD, and

VSS power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed

directly under the device using a standard escape pattern. Others may surround the part.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)

capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,

feeding the VDD, NVDD, GVDD, LVDD planes, to enable quick recharging of the smaller chip capacitors.

These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick

response time necessary. They should also be connected to the power and ground planes through two vias

to minimize inductance. Suggested bulk capacitors—100 to 330 µF (AVX TPS tantalum or Sanyo

OSCON). However, customers should work directly with their power regulator vendor for best values and

types of bulk capacitors.

23.4

Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal

level. Unused active low inputs should be tied to NVDD, GVDD, LVDD as required. Unused active high

inputs should be connected to VSS. All NC (no-connect) signals must remain unconnected.

Power and ground connections must be made to all external VDD, NVDD, AVDD1, AVDD2, GVDD, LVDD

and VSS pins of the device.

23.5

Output Buffer DC Impedance

The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a

push-pull single-ended driver type (open drain for I2C, MDIO and HRESET)

To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to NVDD

or VSS. Then, the value of each resistor is varied until the pad voltage is NVDD/2 (Figure 55). The output

impedance is the average of two components, the resistances of the pull-up and pull-down devices. When

data is held high, SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals

NVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each

other in value. Then, Z0 = (RP + RN)/2.

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