HT95R45 datasheet(33/76 Pages) HOLTEK

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HT95R45

Rev. 1.00

March 12, 2010

CKPOL

CKEG

SCK Clock Signal

High Base Level

Active Rising Edge

High Base Level

Active Falling Edge

Low Base Level

Active Falling Edge

Low Base Level

Active Rising Edge

SPI Communication

After the SPI interface is enabled by setting the SIMEN

bit high, then in the Master Mode, when data is written to

the SIMDR register, transmission/reception will begin si-

multaneously. When the data transfer is complete, the

TRF flag will be set automatically, but must be cleared

using the application program. In the Slave Mode, when

the clock signal from the master has been received, any

data in the SIMDR register will be transmitted and any

data on the SDI pin will be shifted into the SIMDR regis-

ter. The master should output an SCS signal to enable

the slave device before a clock signal is provided and

slave data transfers should be enabled/disabled be-

fore/after an SCS signal is received.

The SPI will continue to function even after a HALT in-

struction has been executed.

2C Interface

The I

2C interface is used to communicate with external

peripheral devices such as sensors, EEPROM memory

etc. Originally developed by Philips, it is a two line low

speed serial interface for synchronous serial data trans-

fer. The advantage of only two lines for communication,

relatively simple communication protocol and the ability

to accommodate multiple devices on the same bus has

made it an extremely popular interface type for many

applications.

· I2C Interface Operation

The I

2C serial interface is a two line interface, a serial

data line, SDA, and serial clock line, SCL. As many

devices may be connected together on the same bus,

their outputs are both open drain types. For this rea-

son it is necessary that external pull-high resistors are

connected to these outputs. Note that no chip select

line exists, as each device on the I

2C bus is identified

by a unique address which will be transmitted and re-

ceived on the I

2C bus.

When two devices communicate with each other on

the bidirectional I

2C bus, one is known as the master

device and one as the slave device. Both master and

slave can transmit and receive data, however, it is the

master device that has overall control of the bus. For

these devices, which only operates in slave mode,

there are two methods of transferring data on the I

bus, the slave transmit mode and the slave receive

mode.

There are several configuration options associated

with the I

2C interface. One of these is to enable the

function which selects the SIM pins rather than normal

I/O pins. Note that if the configuration option does not

select the SIM function then the SIMEN bit in the

SIMCTL0 register will have no effect. A configuration

option exists to allow a clock other than the system

clock to drive the I

2C interface. Another configuration

option determines the debounce time of the I

2C inter-

face. This uses the internal clock to in effect add a

debounce time to the external clock to reduce the pos-

sibility of glitches on the clock line causing erroneous

operation. The debounce time, if selected, can be

chosen to be either 1 or 2 system clocks.

SIM

Function

SIM function

SIM interface or SEG pins

2C clock

2C runs without internal clock

Disable/Enable

2C debounce

No debounce, 1 system clock;

2 system clocks

2C Interface Configuration Options

· I2C Registers

There are three control registers associated with the

2C bus, SIMCTL0, SIMCTL1 and SIMAR and one

data register, SIMDR. The SIMDR register, which is

shown in the above SPI section, is used to store the

data being transmitted and received on the I

2C bus.

Before the microcontroller writes data to the I

2C bus,

the actual data to be transmitted must be placed in the

SIMDR register. After the data is received from the I

bus, the microcontroller can read it from the SIMDR

the I

2C bus must be made via the SIMDR register.

Note that the SIMAR register also has the name

SIMCTL2 which is used by the SPI function. Bits

SIMIDLE , SIMEN and bits SIM0~SIM2 in register

SIMCTL0 are used by the I

2C interface. The SIMCTL0

S T A R T s i g n a l

f r o m M a s t e r

S e n d s l a v e a d d r e s s

a n d R / W b i t f r o m M a s t e r

A c k n o w l e d g e

f r o m s l a v e

S e n d d a t a b y t e

f r o m M a s t e r

A c k n o w l e d g e

f r o m s l a v e

S T O P s i g n a l

f r o m M a s t e r

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