HT56R668 datasheet(49/104 Pages) HOLTEK

49 / 104 page

HT56R67/HT56R668/HT56C668/HT56R678/HT56C678/HT56R688

Rev. 1.20

March 4, 2010

The START bit in the register is used to start and reset

the A/D converter. When themicrocontroller sets this bit

from low to high and then low again, an analog to digital

conversion cycle will be initiated. When the START bit is

brought from low to high but not low again, the EOCB bit

in the ADCR register will be set to a

²1² and the analog

to digital converter will be reset. It is the START bit that is

used to control the overall on/off operation of the internal

analog to digital converter.

The EOCB bit in the ADCR register is used to indicate

when the analog to digital conversion process is com-

plete. This bit will be automatically set to

²0² by the

microcontroller after a conversion cycle has ended. In

addition, the corresponding A/D interrupt request flag

will be set in the interrupt control register, and if the inter-

rupts are enabled, an appropriate internal interrupt sig-

nal will be generated. This A/D internal interrupt signal

will direct the program flow to the associated A/D inter-

nal interrupt address for processing. If the A/D internal

interrupt is disabled, the microcontroller can be used to

poll the EOCB bit in the ADCR register to check whether

it has been cleared as an alternative method of detect-

ing the end of an A/D conversion cycle.

The clock source for the A/D converter, which originates

from the system clock fSYS, is first divided by a division

ratio, the value of which is determined by the ADCS2,

ADCS1 and ADCS0 bits in the ACSR register.

Controlling the on/off function of the A/D converter cir-

cuitry is implemented using the ADONB bit in the ACSR

ister. Both the ADONB bit must cleared to

²0² and the

value of the PCR bits must have a non-zero value for the

A/D converter to be enabled.

PCR

ADONB

A/D

Off

> 0

Off

Although the A/D clock source is determined by the sys-

tem clock fSYS, and by bits ADCS2, ADCS1 and ADCS0,

there are some limitations on the maximum A/D clock

source speed that can be selected. As the minimum value

of permissible A/D clock period, tAD,is0.5

ms, care must be

taken for system clock speeds in excess of 4MHz. For

system clock speeds in excess of 4MHz, the ADCS2,

ADCS1 and ADCS0 bits should not be set to

²000². Doing

so will give A/D clock periods that are less than the mini-

mum A/D clock period which may result in inaccurate A/D

conversion values. Refer to the following table for exam-

ples, where values marked with an asterisk * show where,

depending upon the device, special care must be taken,

as the values may be less than the specified minimum A/D

Clock Period.

b 7

b 0

S T A R T

P C R 2 P C R 1 P C R 0 A C S 2 A C S 1 A C S 0

E O C B

A D C R R e g i s t e r

S e l e c t A / D c h a n n e l

P o r t B A / D c h a n n e l c o n f i g u r a t i o n s

E n d o f A / D c o n v e r s i o n f l a g

1 : A / D c o n v e r s i o n w a i t i n g o r i n p r o g r e s s

0 : A / D c o n v e r s i o n e n d e d

S t a r t t h e A / D c o n v e r s i o n

0 ® 1 ® 0 : S t a r t

0 ® 1 : R e s e t A / D c o n v e r t e r a n d s e t E O C B t o " 1 "

A C S 2

A C S 1

A C S 0

A N 0

A N 1

A N 2

A N 3

A N 4

A N 5

A N 6

A N 7

P C R 2

P C R 1

P C R 0

P o r t B A / D c h a n n e l s - a l l o f f

P B 0 e n a b l e d a s A N 0

P B 0 ~ P B 1 e n a b l e d a s A N 0 ~ A N 1

P B 0 ~ P B 2 e n a b l e d a s A N 0 ~ A N 2

P B 0 ~ P B 3 e n a b l e d a s A N 0 ~ A N 3

P B 0 ~ P B 4 e n a b l e d a s A N 0 ~ A N 4

P B 0 ~ P B 5 e n a b l e d a s A N 0 ~ A N 5

P B 0 ~ P B 7 e n a b l e d a s A N 0 ~ A N 7

A/D Converter Control Register

- ADCR

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