HT56R67 datasheet(79/104 Pages) HOLTEK

79 / 104 page

HT56R67/HT56R668/HT56C668/HT56R678/HT56C678/HT56R688

Rev. 1.20

March 4, 2010

An additional sub internal clock, with the internal name

fSUB, is a 32kHz clock source which can be sourced from

either the internal 32K_INT oscillator or an external

32768 Hz crystal, selected by configuration option. To-

gether with fSYS/4, it is used as a clock source for certain

internal functions such as the LCD driver, Watchdog

Timer, Buzzer, RTC Interrupt and Time Base Interrupt.

The LCD clock source is the fSUB clock source divided by

8, giving a frequency of 4kHz. The internal clock fS,is

simply a choice of either fSUB or fSYS/4, using a configura-

tion option.

Operating Modes

After the correct clock source configuration selections

are made, overall operation of the chosen clock is

achieved using the CLKMOD register. A combination of

the HLCLK and IDLEN bits in the CLKMOD register and

use of the HALT instruction determine in which mode the

device will be run. The devices can operate in the follow-

ing Modes.

· Normal mode

fM on, fSLOW on, fSYS=fM, CPU on, fS on, fLCD on/off de-

pending upon the LCDEN bit, fWDT on/off depending

upon the WDT configuration option and WDT control

· Slow mode

fM on, fSLOW=fM/2~fM/64, fSYS=fSLOW, CPU on, fS on, fLCD

on/off depending upon the LCDEN bit, fWDT on/off de-

pending upon the WDT configuration option and WDT

control register.

¢s important to note that fSLOW ³ 100kHz for proper

MCU operation.

· Idle mode

fM,fSLOW,fSYS off, CPU off; fSUB on, fS on/off by selecting

fSUB or fSYS/4, fLCD on/off depending upon the LCDEN

bit, fWDT on/off depending upon the WDT configuration

option and WDT control register.

· Sleep mode

fM,fSLOW,fSYS,fS,fLCD off, CPU off; fSUB,fWDT on/off de-

pending upon the WDT configuration option and WDT

control register.

C L K M O D R e g i s t e r

f S Y S s e l e c t

1 : f M

0 : f S L O W

I d l e m o d e

1 : e n a b l e

0 : d i s a b l e

H i g h o s c i l l a t o r r e a d y f l a g

1 : t i m e - o u t

0 : n o n - t i m e - o u t

L o w o s c i l l a t o r r e a d y f l a g

1 : t i m e - o u t

0 : n o n - t i m e - o u t

S P I / I C c o n t i n u e s r u n n i n g i n I d l e m o d e

1 : e n a b l e

0 : d i s a b l e

f S L O W s e l e c t i o n

b 0

I D L E N

H L C L K

H T O

L T O

b 7

S L O W C 0

S L O W C 1

S L O W C 2

f S L O W

f M / 6 4

f M / 3 2

f M / 1 6

f M / 8

f M / 4

f M / 2

S L O W W C 2

S L O W W C 1

S L O W W C 0

S I M I D L E

Clock Control Register

- CLKMOD

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