Rev 1.00

March 22, 2010

16

HT45B0K

SPI to USB Bridge

PIPE Register

The PIPE register is used to control that the FIFO pipe for each endpoint is enabled or disable. The

endpoint access interrupt can be controlled independently by configuring the UIC register if the

corresponding Endpoint FIFO pipe is enabled.

PIPE Register

Bit

7

6

5

4

3

2

1

0

Name

SUSPC

―

EP5E

EP4E

EP3E

EP2E

EP1E

―

R/W

R/W

―

R/W

R/W

R/W

R/W

R/W

―

POR

0

―

00

00

0

―

Bit 7

SUSPC: USB PHY control in suspend mode

0: the USB PHY is enabled.

1: the USB PHY is disabled.

If the USB enters the suspend mode, user can set SUSPC bit to 1 to disable the USB

PHY for low power consumption. When the USB receives the resume signal from the

USB host, the SUSPC bit should be set to 0 to make sure that the USB PHY can work

normally.

Bit 6

Unimplemented, read as “0”.

Bit 5~1

EP5E~EP1E: USB Endpoint 5 ~ Endpoint 0 FIFO pipe enable control.

0: the corresponding Endpoint FIFO Pipe is disabled.

1: the corresponding Endpoint FIFO Pipe is enabled.

If the corresponding Endpoint FIFO pipe is disabled, the read/write operations to the

related Endpoint FIFO Pipe are not available. If the corresponding Endpoint FIFO

Pipe and the interrupt are both enabled, the related USB Endpoint interrupt will be

generated as the interrupt trigger events occur. Otherwise, if the Endpoint FIFO Pipe

or the Endpoint interrupt is disabled, the corresponding Endpoint interrupt will not be

generated.

Bit 0

Unimplemented, read as “0”.

SWRST register

The SWRST register controls the software reset operation of the device. The only one available

bit named RESET in the SWRST register is the device software reset control bit. When this bit is

equal to “0”, the device operates normally. If this bit is equal to “1”, the whole device will be reset

act just like power-on reset. When this situation occurs, all of the device registers and the circuitry

relevant to SPI interface and USB Module will be reset. The registers in this device including the

status registers and control registers will keep the POR states shown in the above USB registers

summary table after the reset condition occurs.

SWRST Register

Bit

7

6

5

4

3

2

1

0

Name

―

―

――

――

―

RESET

R/W

―

―

――

――

―

R/W

POR

―

―

――

――

―

0

Bit 7~1

Unimplemented, read as “0”.

Bit 0

RESET: device software reset

0: no action

1: device reset occurs